Publications

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2002
O. J. Santana, Falcón, A., Fernández, E., Medina, P., Ramirez, A., and Valero, M., A Comprehensive Analysis of Indirect Branch Prediction, 4th International Symposium on High Performance Computing (ISHPC-4). Springer-Verlag, Kansai Science City (Japan), pp. 133-141, 2002.
A. Ramirez, Santana, O. J., Larriba-Pey, J. L., and Valero, M., Fetching Instruction Streams, 35th Annual International Symposium on Microarchitecture (MICRO-35). Istambul (Turkey), pp. 371-382, 2002.
A. Falcón, Santana, O. J., Medina, P., Fernández, E., Ramirez, A., and Valero, M., Studying New Ways for Improving Adaptive History Length Branch Predictors, 4th International Symposium on High Performance Computing (ISHPC-4). Kansai Science City (Japan), pp. 271-279, 2002.
2003
O. J. Santana, Galluzzi, M., Ramirez, A., and Valero, M., An Analysis of Dynamic Instruction Streams, XIV Jornadas de Paralelismo. Leganés (Spain), pp. 527-532, 2003.
O. J. Santana, Ramirez, A., and Valero, M., Latency Tolerant Branch Predictors, 2003 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'03). Kauai, Hawaii (United States), pp. 30-39, 2003.
A. Falcón, Santana, O. J., Ramirez, A., and Valero, M., Tolerating branch predictor latency on SMT, 5th International Symposium on High Performance Computing (ISHPC-V). Tokio (Japan), pp. 86-98, 2003.
2004
O. J. Santana, Falcón, A., Ramirez, A., and Valero, M., A Complexity-Effective Decoding Architecture Based on Instruction Streams, Workshop on Complexity-Effective Design (WCED). 2004.
A. Cristal, Santana, O. J., and Valero, M., A Comprehensive Description of Kilo-Instruction Processors, 5o Congreso Nacional de Computación. Instituto Politécnico Nacional - Centro de Investigación en Computación, Mexico City, Mexico, pp. 144–154, 2004.
M. Galluzzi, Puente, V., Santana, O. J., Acosta, C., Cristal, A., Beivide, R., Monasterio, J. A. G., and Valero, M., Introducing Kilo-instruction Multiprocessors, XV Jornadas de Paralelismo. Universidad de Almería, Servicio de Publicaciones, Almería, Spain, 2004.
A. Falcón, Santana, O. J., Ramirez, A., and Valero, M., A latency conscious SMT branch predictor architecture, International Journal of High Performance Computing and Networking (IJHPCN), vol. 2, no. 1. pp. 11-21, 2004.
M. Valero, Santana, O. J., Ramirez, A., and Larriba-Pey, J. L., A Low Complexity Fetch Architecture for High Performance Superscalar Processors, ACM Transactions on Architecture and Compiler Optimizations (TACO), vol. 1, no. 2. pp. 220-245, 2004.
O. J. Santana, Ramirez, A., Larriba-Pey, J. L., and Valero, M., A Low-Complexity Fetch Architecture for High-Performance Superscalar Processors, ACM Transactions on Architecture and Code Optimization, vol. 1, no. 2. pp. 220-245, 2004.
A. Cristal, Santana, O. J., and Valero, M., Maintaining Thousands of In-Flight Instructions, 10th International Euro-Par 2004 Conference. Springer-Verlag, Pisa, Italy, pp. 9–20, 2004.
O. J. Santana, Ramirez, A., and Valero, M., Reducing Fetch Architecture Complexity Using Procedure Inlining, 8th Workshop on Interaction between Compilers and Computer Architectures (INTERACT). 2004.
A. Falcón, Santana, O. J., Ramirez, A., and Valero, M., Selecting Where to Simulate SPEC2000 Using Streams Analysis, XV Jornadas de Paralelismo. p. 208--213, 2004.
O. J. Santana, Falcón, A., Ramirez, A., and Valero, M., Stream Predictor Guided Instruction Decoding, XV Jornadas de Paralelismo. pp. 184-189, 2004.
A. Cristal, Santana, O. J., Valero, M., and Martínez, J. F., Toward Kilo-instruction Processors, ACM Transactions on Architecture and Code Optimization, vol. 1, pp. 368–396, 2004.
2006
O. J. Santana, Falcón, A., Ramirez, A., and Valero, M., Branch Predictor Guided Instruction Decoding, IEEE Intl. Conference on Parallel Architectures and Compiler Techniques (PACT-2006). 2006.
I. González, Santana, O. J., Pajuelo, A., and Valero, M., A First Glance at the Implementation of Precise Recoveries in Out-of-order Commit Processors. ACACES 2006, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, 2006.
I. González, Santana, O. J., Pajuelo, A., and Valero, M., Implementando recuperaciones precisas en procesadores con consolidación fuera de orden. XVII Jornadas de Paralelismo, 2006.
T. Ramírez, Cristal, A., Santana, O. J., Pajuelo, A., and Valero, M., Kilo-Instruction Processors, RunAhead and Prefetch, ACM International Conference on Computing Frontiers (CF 2006). ACM Press, Ischia, Italy, 2006.
T. Ramírez, Pajuelo, M., Santana, O. J., and Valero, M., Kilo-instruction Processors, Runahead and Prefetching. ACM International Conference on Computing Frontiers, 2006.
J. Vera, Cazorla, F., Pajuelo, A., Santana, O. J., Fernández, E., and Valero, M., Looking for novel ways to obtain fair measurements in multithreaded architectures. XVII Jornadas de Paralelismo, 2006.
J. Vera, Cazorla, F., Pajuelo, A., Santana, O. J., Fernández, E., and Valero, M., A Novel Evaluation Methodology to Obtain Fair Measurements in Multithreaded Architectures. In Workshop on Modeling, Benchmarking and Simulation (MoBS)2006. Held in conjunction with ISCA, Boston, USA, 2006.
T. Ramírez, Pajuelo, M., Santana, O. J., and Valero, M., A Simple Speculative Load Control Mechanism for Energy Saving. MEDEA Workshop: ?MEmory performance:DEaling with Applications, systems and architecture?, 2006.
2011
T. Ramírez, Santana, O. J., Pajuelo, A., and Valero, M., Efficient runahead threads. PACT 2010. International Conference on Parallel Architectures and Compiler Techniques, 2011.