Publications

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2004
Pajuelo, A., González, A. & Valero, M. Aggressive Speculative Execution for Hidding Memory Latency. (2004).
March, M., García, J., Cerdá, L. & Valero, M. Analysis of a high performance DRAM/SRAM memory scheme for fast packet buffers. (2004).
Verdú, J., García, J., Nemirovsky, M. & Valero, M. Analysis of Traffic Traces for Stateful Applications. (2004).
Verdú, J., García, J., Nemirovsky, M. & Valero, M. Analysis of Traffic Traces for Statefull Applications. (2004).
Cazorla, F., Fernández, E., Ramirez, A. & Valero, M. Approaching a Smart Sharing of Resources in SMT Processors. Workshop on Complexity-Effective Design (WCED) (2004).
Pericàs, M., González, R., Cristal, A., Veidenbaum, A. & Valero, M. Banked Front-End Register File. (2004).
Cristal, A., Martínez, J. F., Llosa, J. & Valero, M. A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors. ACM SIGARCH Computer Architecture News 32, 3–10 (2004).
González, R., Cristal, A., Veidenbaum, A., Pericàs, M. & Valero, M. A clustered Processor based on Content-Aware Register File. (2004).
Santana, O. J., Falcón, A., Ramirez, A. & Valero, M. A Complexity-Effective Decoding Architecture Based on Instruction Streams. Workshop on Complexity-Effective Design (WCED) (2004).
Cristal, A., Santana, O. J. & Valero, M. A Comprehensive Description of Kilo-Instruction Processors. 5o Congreso Nacional de Computación 144–154 (Instituto Politécnico Nacional - Centro de Investigación en Computación, 2004).
González, R., Cristal, A., Ortega, D., Veidenbaum, A. & Valero, M. A Content Aware Integer Register File Organization. International Symposium on Computer Architecture (ISCA 2004) 314–324 (IEEE/ACM Press, 2004). at <http://capinfo.e.ac.upc.edu/PDFs/dir23/file002981.pdf>
Cazorla, F., Fernández, E., Ramirez, A. & Valero, M. DCache Warn: An I-Fetch Policy To Increase SMT Efficiency. 18th International Parallel and Distributed Processing Symposium (IPDPS-2004) (2004).
Ramírez, M. A., Cristal, A., Villa, L. A., Veidenbaum, A. & Valero, M. Direct Instruction Wakeup for OOO processors. Innovative Architecture for Future Generation High-Performance Processors and System (IEEE Computer Society Press, 2004).
Ortega, D., Valero, M. & Ayguadé, E. Dynamic Memory Instruction Bypassing. (2004).
Cazorla, F., Ramirez, A., Valero, M. & Fernández, E. Dynamically Controlled Resource Allocation in SMT Processors. 37th Annual International Symposium on Microarchitecture (MICRO-37) 171-182 (2004).
Cazorla, F. et al. Enabling SMT for Real-Time Embedded Systems. European Signal Processing Conference (EUSIPCO) (2004).
Galluzzi, M. et al. Evaluating Kilo-instruction Multiprocessors. 3rd Workshop on Memory Performance Issues (WMPI-2004) 72–79 (ACM Press, 2004). at <http://capinfo.e.ac.upc.edu/PDFs/dir21/file002979.pdf>
Cazorla, F. et al. Feasibility of QoS for SMT by Resource Allocation. Lecture Notes in Computer Science (LNCS) 3149/2004, (2004).
Galluzzi, M. et al. A first glance at Kilo-instruction based multiprocessors. International Conference on Computing Frontiers 2004 (CF'04) 212–221 (ACM Press, 2004). at <http://capinfo.e.ac.upc.edu/PDFs/dir20/file002978.pdf>
Cristal, A., Llosa, J., Valero, M. & Ortega, D. Future ILP processors. International Journal of High Performance Computing and Networking 2, 1–10 (2004).
Acosta, C., Falcón, A., Ramirez, A. & Valero, M. Heterogeneity-Aware Architectures. XV Jornadas de Paralelismo 202-207 (2004).
Pericas, M., Ayguadé, E., Zalamea, J., Llosa, J. & Valero, M. High Performance and Low Power VLIW for Numerical Applications. (2004).
García, J., March, M., Cerdá, L., Corbal, J. & Valero, M. A Hybrid DRAM/SRAM Design for Fast Packet Buffers. (2004).
Cazorla, F. et al. Implicit vs. Explicit Resource Allocation in SMT Processors. 2004 Euromicro Symposium on Digital Systems Design (DSD 2004) 44-51 (2004).
Salami, E. & Valero, M. Initial Evaluation of Multimedia Extensions on VLIW Architectures. (2004).
Ramírez, M. A., Cristal, A., Villa, L. A., Veidenbaum, A. & Valero, M. CIC,s Research and Computing Science (2004).
Galluzzi, M. et al. Introducing Kilo-instruction Multiprocessors. XV Jornadas de Paralelismo (Universidad de Almería, Servicio de Publicaciones, 2004). at <http://capinfo.e.ac.upc.edu/PDFs/dir19/file002977.pdf>
Monreal, T., Viñals, V., González, J., González, A. & Valero, M. Late Allocation and Early Release of Physical Registers. (2004).
Falcón, A., Santana, O. J., Ramirez, A. & Valero, M. A latency conscious SMT branch predictor architecture. International Journal of High Performance Computing and Networking (IJHPCN) 2, 11-21 (2004).
Alastruey, J. J., Monreal, T., Viñals, V. & Valero, M. Limits on Early Release of Physical Registers. (2004).
Valero, M., Santana, O. J., Ramirez, A. & Larriba-Pey, J. L. A Low Complexity Fetch Architecture for High Performance Superscalar Processors. ACM Transactions on Architecture and Compiler Optimizations (TACO) 1, 220-245 (2004).
Santana, O. J., Ramirez, A., Larriba-Pey, J. L. & Valero, M. A Low-Complexity Fetch Architecture for High-Performance Superscalar Processors. ACM Transactions on Architecture and Code Optimization 1, 220-245 (2004).
Falcón, A., Ramirez, A. & Valero, M. A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors. 10th International Conference on High Performance Computer Architecture (HPCA-10) 244-253 (2004).
Cristal, A., Santana, O. J. & Valero, M. Maintaining Thousands of In-Flight Instructions. 10th International Euro-Par 2004 Conference 9–20 (Springer-Verlag, 2004).
Pericàs, M., González, R., Cristal, A., Veidenbaum, A. & Valero, M. An Optimized Front-End Physical Register File with Banking and Writeback Filtering. Workshop on Power-Aware Computer Systems (PACS'04) 4–13 (2004).
Cazorla, F., Fernández, E., Ramirez, A. & Valero, M. Optimizing Long-Latency-Load-Aware Fetch Policies for SMT Processors. International Journal of High Performance Computing and Networking (IJHPCN) 2, (2004).
Cristal, A., Ortega, D., Llosa, J. & Valero, M. Out-of-Order Commit Processors. 10th International Symposium on High Performance Computer Architecture (HPCA-10) 48–59 (IEEE Computer Society Press, 2004).
Ramírez, M. A., Cristal, A., Valero, M., Veidenbaum, A. & Villa, L. A. A partitioned instruction queue to reduce instruction wakeup energy. International Journal of High Performance Computing and Networking 1, 153–161 (2004).
Pericas, M., Ayguadé, E., Zalamea, J., Llosa, J. & Valero, M. Performance and Power Evaluation of Clustered VLIW Processors with Functional Units. (2004).
Cazorla, F. et al. Predictable Performance in SMT Processors. Computing Frontiers (CF'04) (2004).
Falcón, A., Stark, J., Ramirez, A., Lai, K. & Valero, M. Prophet/Critic Hybrid Branch Prediction. 31st Annual International Symposium on Computer Architecture (ISCA-31) 250-262 (2004).
Cazorla, F. et al. QoS for High-Performance SMT Processors in Embedded Systems. IEEE Micro 24, 24-31 (2004).
Santana, O. J., Ramirez, A. & Valero, M. Reducing Fetch Architecture Complexity Using Procedure Inlining. 8th Workshop on Interaction between Compilers and Computer Architectures (INTERACT) (2004).

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