Publications

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2005
C. Acosta, Falcón, A., Ramirez, A., and Valero, M., A Complexity-Effective Simultaneous Multithreading Architecture, 34th International Conference on Parallel Processing (ICPP 2005). 2005.
C. Acosta, Falcón, A., Ramirez, A., and Valero, M., Complexity-Effectiveness in Multithreading Architectures, In 2005 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-2005). L'Aquila (Italy), pp. 79-82, 2005.
A. Pajuelo, González, A., and Valero, M., Control-Flow Independence Reuse via Dynamic Vectorization. IPDPS05, IEEE-ACM 19th International Parallel and Distributed Processing Symposium, 2005.
M. Pericàs, Cristal, A., González, R., and Valero, M., Decoupled State-Execute Architecture, in 6th International Symposium on High Performance Computing (ISHPC-VI 2005), Nara, Japan, 2005, pp. 68–78.
T. Ramírez, Galluzzi, M., Cristal, A., and Valero, M., Different approaches using Kilo-instruction Processors, in 2005 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-2005), L'Aquila, Italy, 2005.
E. Salami and Valero, M., Dynamic Memory Interval Test vs. Interprocedural Pointer Analiysis in Multimedia Applications. ACM Transactions on Architecture and Code Optimization, TACO Journal, 2005.
F. Cazorla, Fernández, E., Ramirez, A., and Valero, M., Dynamically Controlled Resource Allocation in SMT, XVI Jornadas de Paralelismo. Granada. 2005.
A. Falcón, Ramirez, A., and Valero, M., Effective Instruction Prefetching via Fetch Prestaging, IPDPS05. IEEE-ACM 19th International Parallel and Distributed Processing Symposium. 2005.
J. J. Alastruey, Monreal, T., Viñals, V., and Valero, M., Efficient Register File Management in High-ILP Processors. ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, 2005.
T. Ramírez, Cristal, A., Pajuelo, A., Santana, O. J., and Valero, M., Eficacia vs. Eficiencia: Una decisión de diseño en Runahead, in XVI Jornadas de Paralelismo, Granada, Spain, 2005.
M. Pericàs, Cristal, A., González, R., Jiménez, D. A., and Valero, M., Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor, in 6th International Symposium on High Performance Computing (ISHPC-VI 2005), Nara, Japan, 2005, pp. 56–67.
C. Álvarez, Corbal, J., and Valero, M., Fuzzy Memoization for Floating Point Multimedia Applications. IEEE Transactions on Computers, 2005.
T. Monreal, Viñals, V., González, A., and Valero, M., Hardware Support for Early Register Release. IJHPCN. International Journal on High Performance and Networking, 2005.
C. Acosta, Falcón, A., Ramirez, A., and Valero, M., hdSMT: An Heterogeneity-Aware Simultaneous Multithreaded Architecture, XVI Jornadas de Paralelismo. pp. 59-66, 2005.
M. Moreto, Martínez, C., Beivide, R., Vallejo, E., and Valero, M., Hierarchical Gaussian Topologies. ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, 2005.
M. Moreto, Martínez, C., Vallejo, E., Beivide, M., and Valero, M., Hierarchical Topologies for Large-Scale Two-Level Networks. XVI Jornadas de Paralelismo, 2005.
E. Vallejo, Galluzzi, M., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J. E., and Valero, M., Implementing Kilo-Instruction Multiprocessors, in International Conference on Pervasive Services (ICPS 2005), Santorini, Greece, 2005, pp. 325–336.
A. Cristal, Santana, O. J., Cazorla, F., Galluzzi, M., Ramírez, T., Pericàs, M., and Valero, M., Kilo-instruction Processors: Overcoming the Memory Wall, IEEE Micro, vol. 25. pp. 48–57, 2005.
E. Vallejo, Galluzzi, M., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J. E., and Valero, M., KIMP: Multicheckpointing Multiprocessors, in XVI Jornadas de Paralelismo, Granada, Spain, 2005.
S. Mir, Cazorla, F., Ramirez, A., and Valero, M., Metrics for the Evaluation of SMT Processors Performance, XVI Jornadas de Paralelismo. 2005.
O. J. Santana, Ramirez, A., and Valero, M., Multiple Stream Prediction, ISHPC. International Symposium on High Performance Computers. Springer-Verlag, 2005.
M. A. Ramírez, Cristal, A., Valero, M., Veidenbaum, A., and Villa, L. A., A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation, in IEEE International Conference on Computer Design (ICCD-2005), San José, CA, United States, 2005, pp. 647–653.
M. Pericàs, González, R., Cristal, A., and Valero, M., Overcoming the Memor Wall with D-KIPs, in 2005 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-2005), L'Aquila, Italy, 2005, pp. 99–102.
F. Sánchez, Salami, E., Ramirez, A., and Valero, M., Parallel Processing in Biological Sequence Comparison using General Purpose Processors, 2005 IEEE International Symposium on Workload Characterization (IISWC-2005). 2005.
E. Salami, Ramirez, A., Sánchez, F., and Valero, M., Parallel Processing in Sequence Matching, ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. 2005.
R. Holanda, Verdú, J., García, J., and Valero, M., Performance Analysis of New Packet Trace Compression TCP Flow Clustering. ISPASS05. IEEE International Symposium on Performance Analisys of Systems and Software, 2005.
M. Álvarez, Salami, E., Ramirez, A., and Valero, M., A Performance Characterization of High Definition Digital Video Decoding Using H.264/AVC, 2005 IEEE International Symposium on Workload Characterization (IISWC-2005). IEEE Computer Society Press, pp. 24-33, 2005.
M. Álvarez, Salami, E., Ramirez, A., and Valero, M., A Performance Evaluation of High Definition Digital Video Decoding Using the H.264/AVC Standard, ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. pp. 255-258, 2005.
M. Pericas, Ayguadé, E., Zalamea, J., Llosa, J., and Valero, M., Power and Performace Evaluation of Widened and Clustered VLIW Cores. LNCS, 2005.
O. J. Santana, Ramirez, A., and Valero, M., Predicting two Streams per Cycle, XVI Jornadas de Paralelismo. pp. 3-10, 2005.
F. Cazorla, Knijnenburg, P., Sakellarious, R., Fernández, E., Ramirez, A., and Valero, M., Quality of service for Simultaneous Multithreading Processors, ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. pp. 67-70, 2005.
F. Sánchez, Álvarez, M., Salami, E., Ramirez, A., and Valero, M., On the Scalability of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications, 2005 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2005). pp. 167-176, 2005.
A. Ramirez, Larriba-Pey, J. L., and Valero, M., Software Trace Cache, IEEE Transactions on Computers, vol. 54, no. 1. pp. 22-35, 2005.
A. Pajuelo, González, A., and Valero, M., Speculative Execution for Hiding Memory Latency. Computer Architecture News, 2005.
J. Verdú, Nemirovsky, M., García, J., and Valero, M., Te Impact of Traffic Aggregation on the Memory Performance of Networking Applications. Computer Architecture News, 2005.
A. García, Medina, P., Fernández, E., Santana, O. J., Cristal, A., and Valero, M., Towards the Loop Processor Architecture, in XVI Jornadas de Paralelismo, Granada, Spain, 2005.
E. Salami and Valero, M., A Vector-uSIMD-VLIW Architecture for Multimedia Applications. ICPP, IEEE International Conference on Parallel Processing, 2005.
J. Verdú, Nemirovsky, M., García, J., and Valero, M., Workload Analysis of Networking Applications. XVI Jornadas de Paralelismo, 2005.
M. Valero, Verdú, J., Nemirovsky, M., and García, J., Workload Characterization and Stateful Networking Aplications. ISHPC. International Symposium on High Performance Computers, 2005.
2004
A. Pajuelo, González, A., and Valero, M., Aggressive Speculative Execution for Hidding Memory Latency. XV Jornadas de Paralelismo, 2004.
M. March, García, J., Cerdá, L., and Valero, M., Analysis of a high performance DRAM/SRAM memory scheme for fast packet buffers. WEPA-1: Workshop on Embedded Parallel Architectures at HPCA-10, 2004.
J. Verdú, García, J., Nemirovsky, M., and Valero, M., Analysis of Traffic Traces for Stateful Applications. NP3 : Third Workshop on Network Processors and Applications at HPCA-10, 2004.
J. Verdú, García, J., Nemirovsky, M., and Valero, M., Analysis of Traffic Traces for Statefull Applications. XV Jornadas de Paralelismo, 2004.
F. Cazorla, Fernández, E., Ramirez, A., and Valero, M., Approaching a Smart Sharing of Resources in SMT Processors, Workshop on Complexity-Effective Design (WCED). 2004.
M. Pericàs, González, R., Cristal, A., Veidenbaum, A., and Valero, M., Banked Front-End Register File. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2004.
A. Cristal, Martínez, J. F., Llosa, J., and Valero, M., A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors, ACM SIGARCH Computer Architecture News, vol. 32, pp. 3–10, 2004.
R. González, Cristal, A., Veidenbaum, A., Pericàs, M., and Valero, M., A clustered Processor based on Content-Aware Register File. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2004.
O. J. Santana, Falcón, A., Ramirez, A., and Valero, M., A Complexity-Effective Decoding Architecture Based on Instruction Streams, Workshop on Complexity-Effective Design (WCED). 2004.
A. Cristal, Santana, O. J., and Valero, M., A Comprehensive Description of Kilo-Instruction Processors, in 5o Congreso Nacional de Computación, Mexico City, Mexico, 2004, pp. 144–154.
R. González, Cristal, A., Ortega, D., Veidenbaum, A., and Valero, M., A Content Aware Integer Register File Organization, in International Symposium on Computer Architecture (ISCA 2004), München, Germany, 2004, pp. 314–324.

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