Publications

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2006
C. Boneti, Cazorla, F., and Valero, M., Improving EDF for SMT processors. XVII Jornadas de Paralelismo, 2006.
M. Valero, Kilo-instruction Processors: Overcoming the Memory Wall. University of Irvine at California, 2006.
T. Ramírez, Cristal, A., Santana, O. J., Pajuelo, A., and Valero, M., Kilo-Instruction Processors, RunAhead and Prefetch, ACM International Conference on Computing Frontiers (CF 2006). ACM Press, Ischia, Italy, 2006.
T. Ramírez, Pajuelo, M., Santana, O. J., and Valero, M., Kilo-instruction Processors, Runahead and Prefetching. ACM International Conference on Computing Frontiers, 2006.
J. Vera, Cazorla, F., Pajuelo, A., Santana, O. J., Fernández, E., and Valero, M., Looking for novel ways to obtain fair measurements in multithreaded architectures. XVII Jornadas de Paralelismo, 2006.
J. J. Alastruey, Monreal, T., Viñals, V., and Valero, M., Microarchitectural Support for Speculative Register Renaming. IPDPS07. IEEE International Parallel and Distributed Processing Sympsium. Long Beach, USA, 2006.
J. Vera, Cazorla, F., Pajuelo, A., Santana, O. J., Fernández, E., and Valero, M., A Novel Evaluation Methodology to Obtain Fair Measurements in Multithreaded Architectures. In Workshop on Modeling, Benchmarking and Simulation (MoBS)2006. Held in conjunction with ISCA, Boston, USA, 2006.
F. Sánchez, Salami, E., Ramirez, A., and Valero, M., Performance Analysis of Sequence Alignment Applications, IISWC, IEEE Internacional Symposium on Workload Characterization. 2006.
T. Morad, Weiser, U., Kolodny, A., Valero, M., and Ayguadé, E., Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors. IEEE CAL, Computer Architecture Letters, 2006.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A., and Valero, M., Predictable Performance in SMT processors: Synergy Between the OS and SMTs, IEEE Transactions on Computers, vol. 55, no. 7. pp. 785-799, 2006.
M. Moreto, Ramirez, A., and Valero, M., Reducing Simulation Time, 2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06). 2006.
T. Ramírez, Pajuelo, M., Santana, O. J., and Valero, M., A Simple Speculative Load Control Mechanism for Energy Saving. MEDEA Workshop: ?MEmory performance:DEaling with Applications, systems and architecture?, 2006.
J. J. Alastruey, Monreal, T., Viñals, V., and Valero, M., Speculative Early Register Release. ACM International Conference on Computing Frontiers, 2006.
2005
M. Valero, Verdú, J., Nemirovsky, M., and García, J., Architectural Impact of Statefull Networking APPlications. ANCS-2005. IEEE and ACM Symposium on Architectures for Networking and Communications Systems, 2005.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A., and Valero, M., Architectural Support for Real-Time Task Scheduling in SMT Processors, International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES-2005). 2005.
R. González, Cristal, A., Pericàs, M., Veidenbaum, A., and Valero, M., Arquitectura Simétrica Clusterizada basada en el Contenido, XVI Jornadas de Paralelismo. Thomson, Granada, Spain, 2005.
R. González, Cristal, A., Pericàs, M., Valero, M., and Veidenbaum, A., An asymetric Clustered Processor Based on Value Content, The 19th ACM International Conference on Supercomputing (ICS'05). ACM Press, Boston, MA, United States, pp. 61–70, 2005.
A. Falcón, Stark, J., Ramirez, A., Lai, K., and Valero, M., Better branch prediction through prophet/critic hybrids, IEEE Micro, vol. 25, no. 1. pp. 80-89, 2005.
C. Acosta, Falcón, A., Ramirez, A., and Valero, M., A Complexity-Effective Simultaneous Multithreading Architecture, 34th International Conference on Parallel Processing (ICPP 2005). 2005.
C. Acosta, Falcón, A., Ramirez, A., and Valero, M., Complexity-Effectiveness in Multithreading Architectures, In 2005 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-2005). L'Aquila (Italy), pp. 79-82, 2005.
A. Pajuelo, González, A., and Valero, M., Control-Flow Independence Reuse via Dynamic Vectorization. IPDPS05, IEEE-ACM 19th International Parallel and Distributed Processing Symposium, 2005.
M. Pericàs, Cristal, A., González, R., and Valero, M., Decoupled State-Execute Architecture, 6th International Symposium on High Performance Computing (ISHPC-VI 2005). Springer-Verlag, Nara, Japan, pp. 68–78, 2005.
T. Ramírez, Galluzzi, M., Cristal, A., and Valero, M., Different approaches using Kilo-instruction Processors, 2005 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-2005). Academia Press, L'Aquila, Italy, 2005.
E. Salami and Valero, M., Dynamic Memory Interval Test vs. Interprocedural Pointer Analiysis in Multimedia Applications. ACM Transactions on Architecture and Code Optimization, TACO Journal, 2005.
F. Cazorla, Fernández, E., Ramirez, A., and Valero, M., Dynamically Controlled Resource Allocation in SMT, XVI Jornadas de Paralelismo. Granada. 2005.
A. Falcón, Ramirez, A., and Valero, M., Effective Instruction Prefetching via Fetch Prestaging, IPDPS05. IEEE-ACM 19th International Parallel and Distributed Processing Symposium. 2005.
J. J. Alastruey, Monreal, T., Viñals, V., and Valero, M., Efficient Register File Management in High-ILP Processors. ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, 2005.
T. Ramírez, Cristal, A., Pajuelo, A., Santana, O. J., and Valero, M., Eficacia vs. Eficiencia: Una decisión de diseño en Runahead, XVI Jornadas de Paralelismo. Thomson, Granada, Spain, 2005.
M. Pericàs, Cristal, A., González, R., Jiménez, D. A., and Valero, M., Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor, 6th International Symposium on High Performance Computing (ISHPC-VI 2005). Springer-Verlag, Nara, Japan, pp. 56–67, 2005.
C. Álvarez, Corbal, J., and Valero, M., Fuzzy Memoization for Floating Point Multimedia Applications. IEEE Transactions on Computers, 2005.
T. Monreal, Viñals, V., González, A., and Valero, M., Hardware Support for Early Register Release. IJHPCN. International Journal on High Performance and Networking, 2005.
C. Acosta, Falcón, A., Ramirez, A., and Valero, M., hdSMT: An Heterogeneity-Aware Simultaneous Multithreaded Architecture, XVI Jornadas de Paralelismo. pp. 59-66, 2005.
M. Moreto, Martínez, C., Beivide, R., Vallejo, E., and Valero, M., Hierarchical Gaussian Topologies. ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, 2005.
M. Moreto, Martínez, C., Vallejo, E., Beivide, M., and Valero, M., Hierarchical Topologies for Large-Scale Two-Level Networks. XVI Jornadas de Paralelismo, 2005.
E. Vallejo, Galluzzi, M., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J. E., and Valero, M., Implementing Kilo-Instruction Multiprocessors, International Conference on Pervasive Services (ICPS 2005). IEEE, Santorini, Greece, pp. 325–336, 2005.
A. Cristal, Santana, O. J., Cazorla, F., Galluzzi, M., Ramírez, T., Pericàs, M., and Valero, M., Kilo-instruction Processors: Overcoming the Memory Wall, IEEE Micro, vol. 25. pp. 48–57, 2005.
E. Vallejo, Galluzzi, M., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J. E., and Valero, M., KIMP: Multicheckpointing Multiprocessors, XVI Jornadas de Paralelismo. Thomson, Granada, Spain, 2005.
S. Mir, Cazorla, F., Ramirez, A., and Valero, M., Metrics for the Evaluation of SMT Processors Performance, XVI Jornadas de Paralelismo. 2005.
O. J. Santana, Ramirez, A., and Valero, M., Multiple Stream Prediction, ISHPC. International Symposium on High Performance Computers. Springer-Verlag, 2005.
M. A. Ramírez, Cristal, A., Valero, M., Veidenbaum, A., and Villa, L. A., A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation, IEEE International Conference on Computer Design (ICCD-2005). IEEE Computer Society Press, San José, CA, United States, pp. 647–653, 2005.
M. Pericàs, González, R., Cristal, A., and Valero, M., Overcoming the Memor Wall with D-KIPs, 2005 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-2005). Academia Press, L'Aquila, Italy, pp. 99–102, 2005.
F. Sánchez, Salami, E., Ramirez, A., and Valero, M., Parallel Processing in Biological Sequence Comparison using General Purpose Processors, 2005 IEEE International Symposium on Workload Characterization (IISWC-2005). 2005.
E. Salami, Ramirez, A., Sánchez, F., and Valero, M., Parallel Processing in Sequence Matching, ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. 2005.
R. Holanda, Verdú, J., García, J., and Valero, M., Performance Analysis of New Packet Trace Compression TCP Flow Clustering. ISPASS05. IEEE International Symposium on Performance Analisys of Systems and Software, 2005.
M. Álvarez, Salami, E., Ramirez, A., and Valero, M., A Performance Characterization of High Definition Digital Video Decoding Using H.264/AVC, 2005 IEEE International Symposium on Workload Characterization (IISWC-2005). IEEE Computer Society Press, pp. 24-33, 2005.
M. Álvarez, Salami, E., Ramirez, A., and Valero, M., A Performance Evaluation of High Definition Digital Video Decoding Using the H.264/AVC Standard, ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. pp. 255-258, 2005.
M. Pericas, Ayguadé, E., Zalamea, J., Llosa, J., and Valero, M., Power and Performace Evaluation of Widened and Clustered VLIW Cores. LNCS, 2005.
O. J. Santana, Ramirez, A., and Valero, M., Predicting two Streams per Cycle, XVI Jornadas de Paralelismo. pp. 3-10, 2005.
F. Cazorla, Knijnenburg, P., Sakellarious, R., Fernández, E., Ramirez, A., and Valero, M., Quality of service for Simultaneous Multithreading Processors, ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. pp. 67-70, 2005.
F. Sánchez, Álvarez, M., Salami, E., Ramirez, A., and Valero, M., On the Scalability of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications, 2005 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2005). pp. 167-176, 2005.

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