Publications

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2008
A. Rico, Ramirez, A., and Valero, M., Task Management Analysis on the Cell BE, XIX Jornadas de Paralelismo, pp. 271-276, Castellón (Spain). pp. 271-276, 2008.
E. Vallejo, Sanyal, S., Harris, T., Vallejo, F., Beivide, R., Unsal, O., Cristal, A., and Valero, M., Towards Fair Scalable Locking, Workshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods (EPHAM 2008). Boston, MA, United States, 2008.
G. Kestor, Unsal, O., Cristal, A., and Valero, M., Transactional Look-based Parallel Program, Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008. HiPEAC Network of Excellence, L'Aquila, Italy, pp. 71–75, 2008.
M. Pericàs, Cristal, A., Cazorla, F., González, R., Veidenbaum, A., Jiménez, D. A., and Valero, M., A Two-Level Load/Store Queue Based on Execution Locality, The 35th International Symposium on Computer Architecture (ISCA 2008). The Institute of Electrical and Electronics Engineers, Inc., Beijing, China, pp. 25–36, 2008.
M. Pericas, González, R., Cazorla, F., Cristal, A., Veidenbaum, A., Jiménez, D. A., and Valero, M., A two-level Load/Store Queue based on Execution Locality. In International Symposium on Computer Architecture. Beijing, China, 2008.
V. Cakarevic, Radojkovic, P., Verdú, J., Pajuelo, A., Gioiosa, R., Cazorla, F., Nemirovsky, M., and Valero, M., Understanding the overhead of the spin-lock loop in CMT architectures. In Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA). Beijing, China, 2008.
M. Pericas, Chaves, R., Gaydadjiev, G. N., Valero, M., and Vassiliadis, S., Vectorized AES Core for high-throughput secure environments. VECPAR'08, 2008.
K. J. Nesbit, Moreto, M., Cazorla, F., Ramirez, A., Valero, M., and Smith, J. E., Virtual Private Machines: Hardware/Software Interactions in the Multicore Era. IEEE Micro, special issue on Interaction of Computer Architecture and Operating System in the Manycore Era, vol. 38, no. 3, 2008.
N. Sönmez, Cristal, A., Unsal, O., Harris, T., and Valero, M., Why you should profile Transactional Memory Applications on an Atomic Block basis: A Haskell Case Study. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, 2008.
F. Zyulkyarov, Cristal, A., Cvijic, S., Ayguadé, E., Valero, M., Unsal, O., and Harris, T., WormBench: a configurable workload for evaluating transactional memory systems, 9th workshop on MEmory performance: DEaling with Applications, systems and architecture (MEDEA 2008). ACM, Toronto, Canada, pp. 61–68, 2008.
2007
M. Milovanovic, Unsal, O., Cristal, A., Stipić, S., Zyulkyarov, F., and Valero, M., Compile time support for using transactional memory in C/C++ applications, The 11th Annual Workshop on the Interaction between Compilers and Computer Architecture (INTERACT-11). Phoenix, AR, United States, pp. 16–23, 2007.
C. Acosta, Cazorla, F., Ramirez, A., and Valero, M., Core to Memory Interconnection Implications for Forthcoming On-Chip Multiprocessors, 1st Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI 2007). 2007.
C. Perfumo, Sönmez, N., Cristal, A., Unsal, O., and Valero, M., Development and Analysis of the Haskell Transactional Memory Benchmark Suite, 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07). Academia Press, L'Aquila, Italy, pp. 139–140, 2007.
C. Perfumo, Sönmez, N., Unsal, O., Cristal, A., Harris, T., and Valero, M., Dissecting Transactional Executions in Haskell, The Second ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2007). Portland, OR, United States, 2007.
E. Lara, Cristal, A., and Valero, M., El Procesador Kilo-Ruanahead, una Alternativa para Reducir el Número de Registros Físicos del Procesador Kilo-Instruction, II Congreso Español de Informática (CEDI 2007). Zaragoza, Spain, 2007.
O. J. Santana, Ramirez, A., and Valero, M., Enlarging Instruction Streams, IEEE Transactions on Computers, vol. 56, no. 10. pp. 1342-1357, 2007.
M. Moreto, Cazorla, F., Ramirez, A., and Valero, M., Explaining Dynamic Cache Partitioning Speed Ups, IEEE Computer Architecture Letters, vol. 6, no. 1. pp. 1-12, 2007.
M. Milovanovic, Unsal, O., Cristal, A., Stipić, S., Zyulkyarov, F., and Valero, M., Extending C/C++ Language with Atomic Constructs, II Congreso Español de Informática (CEDI 2007). Zaragoza, Spain, 2007.
J. Vera, Cazorla, F., Pajuelo, A., Santana, O. J., Fernández, E., and Valero, M., FAME: FAirly MEasuring Multithreaded Architectures. Brasov, Romania, 2007.
M. Pericàs, Cristal, A., Cazorla, F., González, R., Jiménez, D., and Valero, M., A Flexible Heterogeneous Multi-Core Architecture, The 2007 International Conference on Parallel Architectures and Compilation Techniques (PACT 2007). Brasov, Romania, pp. 13–24, 2007.
S. Tomić, Cristal, A., Unsal, O., and Valero, M., Hardware Transactional Memory with Operating System Support, HTMOS, Workshop on Highly Parallel Processing on a Chip in conjunction with Euro-Par. IRISA, Rennes, France, 2007.
M. Álvarez, Salami, E., Ramirez, A., and Valero, M., HD-VideoBench. A Benchmark for Evaluating High Definition Digital Video Applications, 2007 IEEE International Symposium on Workload Characterization (IISWC-2007). IEEE Computer Society Press, pp. 120-125, 2007.
M. Galluzzi, Vallejo, E., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J. E., and Valero, M., Implicit Transactional Memory in Kilo-Instruction Multiprocessor, The Twelfth Asia-Pacific Computer Systems Architecture Conference (ACSAC 2007). Springer, Seoul, South Korea, pp. 339–353, 2007.
N. Sönmez, Perfumo, C., Stipić, S., Cristal, A., Unsal, O., and Valero, M., Increasing the Performance of Haskell Software Transactional Memory, II Congreso Español de Informática (CEDI 2007). Zaragoza, Spain, 2007.
J. Vera, Cazorla, F., Pajuelo, A., Santana, O. J., Fernández, E., and Valero, M., Measuring the Performance of Multithreaded Processors. In SPEC Benchmark Workshop (in conjunction with the Annual Meeting of the Standard Performance Evaluation Corporation (SPEC)), Austin, USA, 2007.
F. Zyulkyarov, Unsal, O., Cristal, A., Milovanovic, M., Ayguadé, E., and Valero, M., Memory Management for Transaction Processing Core in Heterogeneous Chip Multiprocessors, Workshop on Operating System Support for Heterogeneous Multicore Architectures. Brasov, Romania, 2007.
M. Moreto, Cazorla, F., Ramirez, A., and Valero, M., MLP-aware dynamic cache partitioning, International Conference on Parallel Architectures and Compilation Techniques (PACT). Brasov, Romania, pp. 418-418, 2007.
I. González, Galluzzi, M., Cristal, A., and Valero, M., The Multi-State Processor, 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07). Academia Press, L'Aquila, Italy, pp. 127–130, 2007.
I. González, Galluzzi, M., Cristal, A., and Valero, M., Multi-State Processor: Arquitectura sin ROB y con recuperaciones Precisas, II Congreso Español de Informática (CEDI 2007). Zaragoza, Spain, 2007.
M. Milovanovic, Ferrer, R., Gajinov, V., Unsal, O., Cristal, A., Ayguadé, E., and Valero, M., Multithreaded software transactional memory and OpenMP, 8th MEDEA Workshop Memory Performance: Dealing With Applications, Systems And Architecture (MEDEA 2007). ACM, Brasov, Romania, pp. 81–88, 2007.
M. Moreto, Cazorla, F., Ramirez, A., and Valero, M., Online Prediction of Applications Cache Utility, International Symposium on Systems, Architectures, MOdeling and Simulation (SAMOS). IEEE Computer Society Press, pp. 169-177, 2007.
M. Moreto, Cazorla, F., Ramirez, A., and Valero, M., Online Prediction of Throughput for Different Cache Sizes, XVIII Jornadas de Paralelismo. Zaragoza, Spain, 2007.
A. Ramirez, Prat, O., Labarta, J., and Valero, M., Performance Impact of the Interconnection Network on MareNostrum Applications, 1st Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC 2007). 2007.
M. Álvarez, Salami, E., Labarta, J., and Valero, M., Performance Impact of Unaligned memory Operations in SIMD Extensions for Video CODEC Applications, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2007). San José, California, USA., pp. 62-71, 2007.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A., and Valero, M., On the Problem of Minimizing Workload Execution Time in SMT Processors, International Conference on Embedded Computer Systems: Architectures, Modelling, and Simulation (SAMOS VII). Samos, Greece, pp. 66-73, 2007.
A. García, Santana, O. J., Fernández, E., Medina, P., Cristal, A., and Valero, M., Reducing the Activity of Instruction Renaming in Loop Structures, II Congreso Español de Informática (CEDI 2007). Zaragoza, Spain, 2007.
F. Zyulkyarov, Unsal, O., Cristal, A., and Valero, M., Synthetic Workloads for Transactional Memory, 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07). Academia Press, L'Aquila, Italy, pp. 135–137, 2007.
T. Harris, Cristal, A., Unsal, O., Ayguadé, E., Galiardi, F., Smith, B., and Valero, M., Transactional Memory: An Overview, IEEE Micro, vol. 27, pp. 8–29, 2007.
M. Milovanovic, Ferrer, R., Unsal, O., Cristal, A., Martorell, X., Ayguadé, E., Labarta, J., and Valero, M., Transactional Memory and OpenMP, International Workshop on OpenMP (IWOMP-2007). Springer-Verlag, Beijing, China, pp. 37–53, 2007.
N. Sönmez, Perfumo, C., Stipić, S., Unsal, O., Cristal, A., and Valero, M., UnreadTVar: Extending Haskell Software Transactional Memory for Performance, The 8th Symposium on Trends in Functional Programming (TFP 2007). New York, United States, pp. 1–11, 2007.
2006
K. Kedzierski, Cazorla, F., and Valero, M., Analysis of multithreading capabilities of current high-performance processors. XVII Jornadas de Paralelismo, 2006.
K. Kedzierski, Cazorla, F., and Valero, M., Analysis of Simultaneous Multithreading Implementations in Current High-Performance Processors. ACACES 2006, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, 2006.
M. Pericàs, Cristal, A., González, R., Cazorla, F., Jiménez, D. A., and Valero, M., Boosting ILP{&}TLP with the Flexible Multi-Core (FMC), 2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06). Academia Press, L'Aquila, Italy, pp. 125–128, 2006.
O. J. Santana, Falcón, A., Ramirez, A., and Valero, M., Branch Predictor Guided Instruction Decoding, IEEE Intl. Conference on Parallel Architectures and Compiler Techniques (PACT-2006). 2006.
E. Vallejo, Galluzzi, M., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J. E., and Valero, M., Chip Multiprocessors with Implicit Transactions, 2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06). Academia Press, L'Aquila, Italy, pp. 167–170, 2006.
M. Pericàs, Cristal, A., González, R., Jiménez, D., and Valero, M., A decoupled KILO-instruction processor, The 12th International Symposium on High-Performance Computer Architecture (HPCA-12). IEEE Press, Auctin, TX, United States, pp. 53–64, 2006.
J. Vidal, March, M., Cerdá, L., Corbal, J., and Valero, M., A DRAM/SRAM Memory Scheme for Fast Packet Buffers. IEEE Transactions on Computers, 2006.
B. Slamat, Nicolaescu, D., Veidenbaum, A., and Valero, M., Fast Speculative Address generation and Way Caching for Reducing L1 data Cache Energy. IEEE ICCD Internation Conference on Computer Design, 2006.
I. González, Santana, O. J., Pajuelo, A., and Valero, M., A First Glance at the Implementation of Precise Recoveries in Out-of-order Commit Processors. ACACES 2006, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, 2006.
I. González, Santana, O. J., Pajuelo, A., and Valero, M., Implementando recuperaciones precisas en procesadores con consolidación fuera de orden. XVII Jornadas de Paralelismo, 2006.

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