Publications

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2006
Slamat, B., Nicolaescu, D., Veidenbaum, A. & Valero, M. Fast Speculative Address generation and Way Caching for Reducing L1 data Cache Energy. (2006).
González, I., Santana, O. J., Pajuelo, A. & Valero, M. A First Glance at the Implementation of Precise Recoveries in Out-of-order Commit Processors. (2006).
González, I., Santana, O. J., Pajuelo, A. & Valero, M. Implementando recuperaciones precisas en procesadores con consolidación fuera de orden. (2006).
Boneti, C., Cazorla, F. & Valero, M. Improving EDF for SMT processors. (2006).
Valero, M. Kilo-instruction Processors: Overcoming the Memory Wall. (2006).
Ramírez, T., Cristal, A., Santana, O. J., Pajuelo, A. & Valero, M. Kilo-Instruction Processors, RunAhead and Prefetch. ACM International Conference on Computing Frontiers (CF 2006) (ACM Press, 2006). at <http://capinfo.e.ac.upc.edu/PDFs/dir05/file003137.pdf>
Ramírez, T., Pajuelo, M., Santana, O. J. & Valero, M. Kilo-instruction Processors, Runahead and Prefetching. (2006).
Vera, J. et al. Looking for novel ways to obtain fair measurements in multithreaded architectures. (2006).
Alastruey, J. J., Monreal, T., Viñals, V. & Valero, M. Microarchitectural Support for Speculative Register Renaming. (2006).
Vera, J. et al. A Novel Evaluation Methodology to Obtain Fair Measurements in Multithreaded Architectures. (2006).
Sánchez, F., Salami, E., Ramirez, A. & Valero, M. Performance Analysis of Sequence Alignment Applications. IISWC, IEEE Internacional Symposium on Workload Characterization (2006).
Morad, T., Weiser, U., Kolodny, A., Valero, M. & Ayguadé, E. Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors. (2006).
Cazorla, F. et al. Predictable Performance in SMT processors: Synergy Between the OS and SMTs. IEEE Transactions on Computers 55, 785-799 (2006).
Moreto, M., Ramirez, A. & Valero, M. Reducing Simulation Time. 2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06) (2006).
Ramírez, T., Pajuelo, M., Santana, O. J. & Valero, M. A Simple Speculative Load Control Mechanism for Energy Saving. (2006).
Alastruey, J. J., Monreal, T., Viñals, V. & Valero, M. Speculative Early Register Release. (2006).
2005
Valero, M., Verdú, J., Nemirovsky, M. & García, J. Architectural Impact of Statefull Networking APPlications. (2005).
Cazorla, F. et al. Architectural Support for Real-Time Task Scheduling in SMT Processors. International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES-2005) (2005).
González, R., Cristal, A., Pericàs, M., Veidenbaum, A. & Valero, M. Arquitectura Simétrica Clusterizada basada en el Contenido. XVI Jornadas de Paralelismo (Thomson, 2005).
González, R., Cristal, A., Pericàs, M., Valero, M. & Veidenbaum, A. An asymetric Clustered Processor Based on Value Content. The 19th ACM International Conference on Supercomputing (ICS'05) 61–70 (ACM Press, 2005). at <http://capinfo.e.ac.upc.edu/PDFs/dir24/file003040.pdf>
Falcón, A., Stark, J., Ramirez, A., Lai, K. & Valero, M. Better branch prediction through prophet/critic hybrids. IEEE Micro 25, 80-89 (2005).
Acosta, C., Falcón, A., Ramirez, A. & Valero, M. A Complexity-Effective Simultaneous Multithreading Architecture. 34th International Conference on Parallel Processing (ICPP 2005) (2005).
Acosta, C., Falcón, A., Ramirez, A. & Valero, M. Complexity-Effectiveness in Multithreading Architectures. In 2005 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-2005) 79-82 (2005).
Pajuelo, A., González, A. & Valero, M. Control-Flow Independence Reuse via Dynamic Vectorization. (2005).
Pericàs, M., Cristal, A., González, R. & Valero, M. Decoupled State-Execute Architecture. 6th International Symposium on High Performance Computing (ISHPC-VI 2005) 68–78 (Springer-Verlag, 2005). at <http://capinfo.e.ac.upc.edu/PDFs/dir15/file003263.pdf>
Ramírez, T., Galluzzi, M., Cristal, A. & Valero, M. Different approaches using Kilo-instruction Processors. 2005 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-2005) (Academia Press, 2005). at <http://capinfo.e.ac.upc.edu/PDFs/dir02/file003076.pdf>
Salami, E. & Valero, M. Dynamic Memory Interval Test vs. Interprocedural Pointer Analiysis in Multimedia Applications. (2005).
Cazorla, F., Fernández, E., Ramirez, A. & Valero, M. Dynamically Controlled Resource Allocation in SMT. XVI Jornadas de Paralelismo. Granada (2005).
Falcón, A., Ramirez, A. & Valero, M. Effective Instruction Prefetching via Fetch Prestaging. IPDPS05. IEEE-ACM 19th International Parallel and Distributed Processing Symposium (2005).
Alastruey, J. J., Monreal, T., Viñals, V. & Valero, M. Efficient Register File Management in High-ILP Processors. (2005).
Ramírez, T., Cristal, A., Pajuelo, A., Santana, O. J. & Valero, M. Eficacia vs. Eficiencia: Una decisión de diseño en Runahead. XVI Jornadas de Paralelismo (Thomson, 2005). at <http://capinfo.e.ac.upc.edu/PDFs/dir01/file003075.pdf>
Pericàs, M., Cristal, A., González, R., Jiménez, D. A. & Valero, M. Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor. 6th International Symposium on High Performance Computing (ISHPC-VI 2005) 56–67 (Springer-Verlag, 2005). at <http://capinfo.e.ac.upc.edu/PDFs/dir16/file003264.pdf>
Álvarez, C., Corbal, J. & Valero, M. Fuzzy Memoization for Floating Point Multimedia Applications. (2005).
Monreal, T., Viñals, V., González, A. & Valero, M. Hardware Support for Early Register Release. (2005).
Acosta, C., Falcón, A., Ramirez, A. & Valero, M. hdSMT: An Heterogeneity-Aware Simultaneous Multithreaded Architecture. XVI Jornadas de Paralelismo 59-66 (2005).
Moreto, M., Martínez, C., Beivide, R., Vallejo, E. & Valero, M. Hierarchical Gaussian Topologies. (2005).
Moreto, M., Martínez, C., Vallejo, E., Beivide, M. & Valero, M. Hierarchical Topologies for Large-Scale Two-Level Networks. (2005).
Vallejo, E. et al. Implementing Kilo-Instruction Multiprocessors. International Conference on Pervasive Services (ICPS 2005) 325–336 (IEEE, 2005).
Cristal, A. et al. Kilo-instruction Processors: Overcoming the Memory Wall. IEEE Micro 25, 48–57 (2005).
Vallejo, E. et al. KIMP: Multicheckpointing Multiprocessors. XVI Jornadas de Paralelismo (Thomson, 2005).
Mir, S., Cazorla, F., Ramirez, A. & Valero, M. Metrics for the Evaluation of SMT Processors Performance. XVI Jornadas de Paralelismo (2005).
Santana, O. J., Ramirez, A. & Valero, M. Multiple Stream Prediction. ISHPC. International Symposium on High Performance Computers (2005).
Ramírez, M. A., Cristal, A., Valero, M., Veidenbaum, A. & Villa, L. A. A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation. IEEE International Conference on Computer Design (ICCD-2005) 647–653 (IEEE Computer Society Press, 2005).
Pericàs, M., González, R., Cristal, A. & Valero, M. Overcoming the Memor Wall with D-KIPs. 2005 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-2005) 99–102 (Academia Press, 2005).
Sánchez, F., Salami, E., Ramirez, A. & Valero, M. Parallel Processing in Biological Sequence Comparison using General Purpose Processors. 2005 IEEE International Symposium on Workload Characterization (IISWC-2005) (2005).
Salami, E., Ramirez, A., Sánchez, F. & Valero, M. Parallel Processing in Sequence Matching. ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems (2005).
Holanda, R., Verdú, J., García, J. & Valero, M. Performance Analysis of New Packet Trace Compression TCP Flow Clustering. (2005).
Álvarez, M., Salami, E., Ramirez, A. & Valero, M. A Performance Characterization of High Definition Digital Video Decoding Using H.264/AVC. 2005 IEEE International Symposium on Workload Characterization (IISWC-2005) 24-33 (2005).
Álvarez, M., Salami, E., Ramirez, A. & Valero, M. A Performance Evaluation of High Definition Digital Video Decoding Using the H.264/AVC Standard. ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems 255-258 (2005).
Pericas, M., Ayguadé, E., Zalamea, J., Llosa, J. & Valero, M. Power and Performace Evaluation of Widened and Clustered VLIW Cores. (2005).

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