Publications

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2007
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A., and Valero, M., On the Problem of Minimizing Workload Execution Time in SMT Processors, International Conference on Embedded Computer Systems: Architectures, Modelling, and Simulation (SAMOS VII). Samos, Greece, pp. 66-73, 2007.
A. García, Santana, O. J., Fernández, E., Medina, P., Cristal, A., and Valero, M., Reducing the Activity of Instruction Renaming in Loop Structures, in II Congreso Español de Informática (CEDI 2007), Zaragoza, Spain, 2007.
F. Zyulkyarov, Unsal, O., Cristal, A., and Valero, M., Synthetic Workloads for Transactional Memory, in 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07), L'Aquila, Italy, 2007, pp. 135–137.
T. Harris, Cristal, A., Unsal, O., Ayguadé, E., Galiardi, F., Smith, B., and Valero, M., Transactional Memory: An Overview, IEEE Micro, vol. 27, pp. 8–29, 2007.
M. Milovanovic, Ferrer, R., Unsal, O., Cristal, A., Martorell, X., Ayguadé, E., Labarta, J., and Valero, M., Transactional Memory and OpenMP, in International Workshop on OpenMP (IWOMP-2007), Beijing, China, 2007, pp. 37–53.
N. Sönmez, Perfumo, C., Stipić, S., Unsal, O., Cristal, A., and Valero, M., UnreadTVar: Extending Haskell Software Transactional Memory for Performance, in The 8th Symposium on Trends in Functional Programming (TFP 2007), New York, United States, 2007, pp. 1–11.
2006
K. Kedzierski, Cazorla, F., and Valero, M., Analysis of multithreading capabilities of current high-performance processors. XVII Jornadas de Paralelismo, 2006.
K. Kedzierski, Cazorla, F., and Valero, M., Analysis of Simultaneous Multithreading Implementations in Current High-Performance Processors. ACACES 2006, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, 2006.
M. Pericàs, Cristal, A., González, R., Cazorla, F., Jiménez, D. A., and Valero, M., Boosting ILP{&}TLP with the Flexible Multi-Core (FMC), in 2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06), L'Aquila, Italy, 2006, pp. 125–128.
O. J. Santana, Falcón, A., Ramirez, A., and Valero, M., Branch Predictor Guided Instruction Decoding, IEEE Intl. Conference on Parallel Architectures and Compiler Techniques (PACT-2006). 2006.
E. Vallejo, Galluzzi, M., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J. E., and Valero, M., Chip Multiprocessors with Implicit Transactions, in 2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06), L'Aquila, Italy, 2006, pp. 167–170.
M. Pericàs, Cristal, A., González, R., Jiménez, D., and Valero, M., A decoupled KILO-instruction processor, in The 12th International Symposium on High-Performance Computer Architecture (HPCA-12), Auctin, TX, United States, 2006, pp. 53–64.
J. Vidal, March, M., Cerdá, L., Corbal, J., and Valero, M., A DRAM/SRAM Memory Scheme for Fast Packet Buffers. IEEE Transactions on Computers, 2006.
B. Slamat, Nicolaescu, D., Veidenbaum, A., and Valero, M., Fast Speculative Address generation and Way Caching for Reducing L1 data Cache Energy. IEEE ICCD Internation Conference on Computer Design, 2006.
I. González, Santana, O. J., Pajuelo, A., and Valero, M., A First Glance at the Implementation of Precise Recoveries in Out-of-order Commit Processors. ACACES 2006, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, 2006.
I. González, Santana, O. J., Pajuelo, A., and Valero, M., Implementando recuperaciones precisas en procesadores con consolidación fuera de orden. XVII Jornadas de Paralelismo, 2006.
C. Boneti, Cazorla, F., and Valero, M., Improving EDF for SMT processors. XVII Jornadas de Paralelismo, 2006.
M. Valero, Kilo-instruction Processors: Overcoming the Memory Wall. University of Irvine at California, 2006.
T. Ramírez, Cristal, A., Santana, O. J., Pajuelo, A., and Valero, M., Kilo-Instruction Processors, RunAhead and Prefetch, in ACM International Conference on Computing Frontiers (CF 2006), Ischia, Italy, 2006.
T. Ramírez, Pajuelo, M., Santana, O. J., and Valero, M., Kilo-instruction Processors, Runahead and Prefetching. ACM International Conference on Computing Frontiers, 2006.
J. Vera, Cazorla, F., Pajuelo, A., Santana, O. J., Fernández, E., and Valero, M., Looking for novel ways to obtain fair measurements in multithreaded architectures. XVII Jornadas de Paralelismo, 2006.
J. J. Alastruey, Monreal, T., Viñals, V., and Valero, M., Microarchitectural Support for Speculative Register Renaming. IPDPS07. IEEE International Parallel and Distributed Processing Sympsium. Long Beach, USA, 2006.
J. Vera, Cazorla, F., Pajuelo, A., Santana, O. J., Fernández, E., and Valero, M., A Novel Evaluation Methodology to Obtain Fair Measurements in Multithreaded Architectures. In Workshop on Modeling, Benchmarking and Simulation (MoBS)2006. Held in conjunction with ISCA, Boston, USA, 2006.
F. Sánchez, Salami, E., Ramirez, A., and Valero, M., Performance Analysis of Sequence Alignment Applications, IISWC, IEEE Internacional Symposium on Workload Characterization. 2006.
T. Morad, Weiser, U., Kolodny, A., Valero, M., and Ayguadé, E., Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors. IEEE CAL, Computer Architecture Letters, 2006.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A., and Valero, M., Predictable Performance in SMT processors: Synergy Between the OS and SMTs, IEEE Transactions on Computers, vol. 55, no. 7. pp. 785-799, 2006.
M. Moreto, Ramirez, A., and Valero, M., Reducing Simulation Time, 2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06). 2006.
T. Ramírez, Pajuelo, M., Santana, O. J., and Valero, M., A Simple Speculative Load Control Mechanism for Energy Saving. MEDEA Workshop: ?MEmory performance:DEaling with Applications, systems and architecture?, 2006.
J. J. Alastruey, Monreal, T., Viñals, V., and Valero, M., Speculative Early Register Release. ACM International Conference on Computing Frontiers, 2006.
2005
M. Valero, Verdú, J., Nemirovsky, M., and García, J., Architectural Impact of Statefull Networking APPlications. ANCS-2005. IEEE and ACM Symposium on Architectures for Networking and Communications Systems, 2005.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A., and Valero, M., Architectural Support for Real-Time Task Scheduling in SMT Processors, International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES-2005). 2005.
R. González, Cristal, A., Pericàs, M., Veidenbaum, A., and Valero, M., Arquitectura Simétrica Clusterizada basada en el Contenido, in XVI Jornadas de Paralelismo, Granada, Spain, 2005.
R. González, Cristal, A., Pericàs, M., Valero, M., and Veidenbaum, A., An asymetric Clustered Processor Based on Value Content, in The 19th ACM International Conference on Supercomputing (ICS'05), Boston, MA, United States, 2005, pp. 61–70.
A. Falcón, Stark, J., Ramirez, A., Lai, K., and Valero, M., Better branch prediction through prophet/critic hybrids, IEEE Micro, vol. 25, no. 1. pp. 80-89, 2005.
C. Acosta, Falcón, A., Ramirez, A., and Valero, M., A Complexity-Effective Simultaneous Multithreading Architecture, 34th International Conference on Parallel Processing (ICPP 2005). 2005.
C. Acosta, Falcón, A., Ramirez, A., and Valero, M., Complexity-Effectiveness in Multithreading Architectures, In 2005 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-2005). L'Aquila (Italy), pp. 79-82, 2005.
A. Pajuelo, González, A., and Valero, M., Control-Flow Independence Reuse via Dynamic Vectorization. IPDPS05, IEEE-ACM 19th International Parallel and Distributed Processing Symposium, 2005.
M. Pericàs, Cristal, A., González, R., and Valero, M., Decoupled State-Execute Architecture, in 6th International Symposium on High Performance Computing (ISHPC-VI 2005), Nara, Japan, 2005, pp. 68–78.
T. Ramírez, Galluzzi, M., Cristal, A., and Valero, M., Different approaches using Kilo-instruction Processors, in 2005 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-2005), L'Aquila, Italy, 2005.
E. Salami and Valero, M., Dynamic Memory Interval Test vs. Interprocedural Pointer Analiysis in Multimedia Applications. ACM Transactions on Architecture and Code Optimization, TACO Journal, 2005.
F. Cazorla, Fernández, E., Ramirez, A., and Valero, M., Dynamically Controlled Resource Allocation in SMT, XVI Jornadas de Paralelismo. Granada. 2005.
A. Falcón, Ramirez, A., and Valero, M., Effective Instruction Prefetching via Fetch Prestaging, IPDPS05. IEEE-ACM 19th International Parallel and Distributed Processing Symposium. 2005.
J. J. Alastruey, Monreal, T., Viñals, V., and Valero, M., Efficient Register File Management in High-ILP Processors. ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, 2005.
T. Ramírez, Cristal, A., Pajuelo, A., Santana, O. J., and Valero, M., Eficacia vs. Eficiencia: Una decisión de diseño en Runahead, in XVI Jornadas de Paralelismo, Granada, Spain, 2005.
M. Pericàs, Cristal, A., González, R., Jiménez, D. A., and Valero, M., Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor, in 6th International Symposium on High Performance Computing (ISHPC-VI 2005), Nara, Japan, 2005, pp. 56–67.
C. Álvarez, Corbal, J., and Valero, M., Fuzzy Memoization for Floating Point Multimedia Applications. IEEE Transactions on Computers, 2005.
T. Monreal, Viñals, V., González, A., and Valero, M., Hardware Support for Early Register Release. IJHPCN. International Journal on High Performance and Networking, 2005.
C. Acosta, Falcón, A., Ramirez, A., and Valero, M., hdSMT: An Heterogeneity-Aware Simultaneous Multithreaded Architecture, XVI Jornadas de Paralelismo. pp. 59-66, 2005.
M. Moreto, Martínez, C., Beivide, R., Vallejo, E., and Valero, M., Hierarchical Gaussian Topologies. ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, 2005.
M. Moreto, Martínez, C., Vallejo, E., Beivide, M., and Valero, M., Hierarchical Topologies for Large-Scale Two-Level Networks. XVI Jornadas de Paralelismo, 2005.

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