Publications

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2011
Araya-Polo, M., Cabezas, J., Hanzich, M., Pericas, M., Morancho, E., Gelado, I., Shafiq, M., Rubio, F., Cela, J.M., Ayguadé, E., Navarro, N. & Valero, M. Assessing Accelerator-based HPC Reverse Time Migration. Transactions on Parallel and Distributed Systems, Special Issue on Accelerators 22(1), 147-162 (2011).
2010
Gelado, I., Stone, J.E., Cabezas, J., Patel, S., Navarro, N. & Hwu, W.-mei An Asymmetric Distributed Shared Memory Model for Heterogeneous Parallel Systems. ACM SIGARCH Computer Architecture News - ASPLOS '10 (2010).at <http://doi.acm.org/10.1145/1735970.1736059>
2009
Cabezas, J., Araya-Polo, M., Gelado, I., Navarro, N. & Cela, J.M. High-Performance Reverse Time Migration on GPU. XXVIII International Conference of the Chilean Computer Society - XIII Workshop on Parallel and Distributed Systems (WSDP) (2009).
Jiménez, V.J., Vilanova, L., Gelado, I., Gil, M., Fursin, G. & Navarro, N. Predictive Runtime Code Scheduling for Heterogeneous Architectures. (2009).at <http://dx.doi.org/10.1007/978-3-540-92990-1_4>
2008
Gelado, I., Kelm, J.H., Ryoo, S., Lumetta, S.S., Navarro, N. & Hwu, W.-mei CUBA: an Architecture for Efficient CPU/co-processor Data Communication. 22nd International Conference on Supercomputing (2008).
Gelado, I., Ramirez, A., Navarro, N. & Villavieja, C. Memory Management on Chip-MultiProcessors with on-chip Memories. Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA'08) 1-7 (2008).
Villavieja, C., Gelado, I., Ramirez, A. & Navarro, N. On-Chip memories, the OS perspective. 5th HiPEAC Industrial Workshop (2008).