Publications

Export 179 results:
Author Title Type [ Year(Asc)]
Filters: Author is Adrián Cristal  [Clear All Filters]
2011
A. Seyedi, Armejach, A., Cristal, A., Unsal, O., Hur, I., and Valero, M., Circuit Design of a Dual-Versioning L1 Data Cache, Integration The VLSI Journal, 2011.
A. Seyedi, Armejach, A., Cristal, A., Unsal, O., Hur, I., and Valero, M., Circuit Design of a Dual-Versioning L1 Data Cache for Optimistic Concurrency, 21st Great Lakes Symposium on Very Large Scale Integration (GLSVLSI'11). Lausanne, Swaziland, 2011.
E. Akpinar, Tomić, S., Cristal, A., Unsal, O., and Valero, M., A Comprehensive Study of Conflict Resolution Policies in Hardware Transactional Memory, 6th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT). San Jose Convention Center, United States, 2011.
C. Villavieja, Karakostas, V., Vilanova, L., Etsion, Y., Ramirez, A., Mendelson, A., Navarro, N., Cristal, A., and Unsal, O., DiDi: Mitigating The Performance Impact of TLB Shootdowns Using A Shared TLB Directory, Parallel Architectures and Compilation Techniques (PACT). Galveston Island, United States, 2011.
G. Yalcin, Unsal, O., Cristal, A., and Valero, M., FaulTM-multi: Fault Tolerance for Multithreaded Applications Running on Transactional Memory Hardware, Workshop on Wild and Sane Ideas in Speculation and Transactions. Galveston Island, TX, United States, 2011.
G. Yalcin, Unsal, O., Cristal, A., and Valero, M., FIMSIM: A fault injection infrastructure for microarchitectural simulators, 29th International Conference on Computer Design (ICCD). Amherst, MA, United States, pp. 431–432, 2011.
O. Arcas, Sönmez, N., Unsal, O., Cristal, A., and Valero, M., A Flexible Hybrid Transactional Memory Multicore on FPGA, Jornadas de Paralelismo 2011. Servicio de Publicaciones. Universidad de La Laguna, Tenerife, 2011, La Laguna, Tenerife, Spain, pp. 283–289, 2011.
N. Sonmez, Arcas, O., Sayilar, G., Unsal, O., Cristal, A., Hur, I., Singh, S., and Valero, M., From plasma to beefarm: Design experience of an FPGA-based multicore prototype, Reconfigurable Computing: Architectures, Tools and Applications. Springer, pp. 350–362, 2011.
N. Sonmez, Arcas, O., Sayilar, G., Unsal, O., Cristal, A., Hur, I., Singh, S., and Valero, M., From Plasma to BeeFarm: Design Experience of an FPGA-based Multicore Prototype, ARC'11. 2011.
N. Sönmez, Arcas, O., Sayilar, G., Cristal, A., Hur, I., Unsal, O., Singh, S., and Valero, M., From Plasma to BeeFarm: Design Experience of an FPGA-based Multicore Prototype, The 7th International Symposium on Applied Reconfigurable Computing (ARC 2011). Belfast, United Kingdom, pp. 1–10, 2011.
V. Gajinov, Cristal, A., Milovanovic, M., Ayguadé, E., Unsal, O., and Valero, M., Integrating dataflow abstractions into transactional memory, Systems for Future Multi-Core Architectures (SFMA'11) . 2011.
V. Gajinov, Milovanovic, M., Unsal, O., Cristal, A., Ayguadé, E., and Valero, M., Integrating Dataflow Abstractions into Transactional Memory, First Workshop on Systems for Future Multi-Core Architectures (SFMA'11). Salzburg, Austria, pp. 1–6, 2011.
G. Kestor, Dalessandro, L., Cristal, A., Scott, M. L., and Unsal, O., Interchangeable Back Ends for STM Compilers, 6th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT). San Jose Convention Center, United States, 2011.
N. Markovic, Nemirovsky, D., González, R., Unsal, O., Valero, M., and Cristal, A., Object Oriented execution Model (OOM), New Directions in Computer Architecture (NDCA-2). San Jose, California, United States, 2011.
N. Markovic, Nemirovsky, D., González, R., Ünsal, O. S., Valero, M., and Cristal, A., Object Orienteed Execution Model (OOM), 2nd Workshop on New Directions in Computer Architecture (NDCA-2) Held in Conjunction with the 38th International Symposium on Computer Architecture (ISCA-38). San Jose, California, Sunday June 5th, 2011.
S. Tomić, Cristal, A., Unsal, O., and Valero, M., Rapid Development of Error-Free Architectural Simulators using Dynamic Runtime Testing, 23rd International Symposium on Computer Architecture and High Performance Computing. Vitória, Espírito Santo, Brazil, 2011.
G. Kestor, Karakostas, V., Unsal, O., Cristal, A., Hur, I., and Valero, M., RMS-TM: A Comprehensive Benchmark Suite for Transactional Memory Systems, International Conference on Performance Engineering (ICPE 2011). ACM, Karlsruhe, Germany, 2011.
G. Kestor, Gioiosa, R., Harris, T., Cristal, A., Unsal, O., Valero, M., and Hur, I., STM2: A Parallel STM for High Performance Simultaneous Multi-Threading Systems, The 20th IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT). 2011.
G. Yalcin, Unsal, O., Cristal, A., Hur, I., and Valero, M., SymptomTM: Symptom Based Error Detection and Recovery Using Hardware Transactional Memory, Parallel Architectures and Compilation Techniques (PACT). Galveston Island, United States, pp. 199–200, 2011.
N. Sönmez, Arcas, O., Pflucker, O., Cristal, A., Unsal, O., Hur, I., Singh, S., and Valero, M., TMbox: A Flexible and Reconfigurable 16-core Hybrid Transactional Memory System, The 19th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2011). Salt Lake City, United States, pp. 1–8, 2011.
N. Sonmez, Arcas, O., Pflucker, O., Unsal, O., Cristal, A., Hur, I., Singh, S., and Valero, M., {TMbox}: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System, Proc. FCCM '11. pp. 146–153, 2011.
N. Sonmez, Arcas, O., Pflucker, O., Unsal, O., Cristal, A., Hur, I., Singh, S., and Valero, M., TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System, Proc. FCCM '11. pp. 146–153, 2011.
T. Hayes, Palomar, O., Unsal, O., Cristal, A., and Valero, M., True Vector Extensions for Decision Support DBMS Acceleration. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, 2011.
A. Armejach, Seyedi, A., Gil, R. T. J., Hur, I., Unsal, O., Cristal, A., and Valero, M., Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory, Parallel Architectures and Compilation Techniques (PACT). Galveston Island, United States, pp. 360–370, 2011.
2010
E. Vallejo, Beivide, R., Cristal, A., Harris, T., Vallejo, F., Unsal, O., and Valero, M., Architectural Support for Fair Reader-Writer Locking, International Symposium on Microarchitecture. Atlanta, United States, 2010.
F. Zyulkyarov, Harris, T., Unsal, O., Cristal, A., and Valero, M., Debugging Programs that use Atomic Blocks and Transactional Memory, 15th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming (PPoPP 2010). Bangalore, India, 2010.
T. Harris, Tomić, S., Cristal, A., and Unsal, O., Dynamic Filtering: Multi-Purpose Architecture Support for Language Runtime Systems, 5th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'10). ACM, Pittsburgh, PA, United States, pp. 39–52, 2010.
G. Yalcin, Unsal, O., Hur, I., and Cristal, A., FaulTM: Fault-Tolerance Using Hardware Transactional Memory, Workshop on Parallel Execution of Sequential Programs on Multi-core Architecture (PESPMA). Saint Malo, French Guiana, 2010.
V. Karakostas, Kestor, G., Unsal, O., Cristal, A., Hur, I., and Valero, M., RMS-TM: A challenging transactional memory benchmark suite, Advanced Computer Architecture and Computation for Embedded Systems (ACACES 2010). Terrassa, Spain, 2010.
A. Armejach, Seyedi, A., Gil, R. T. J., Hur, I., Unsal, O., Cristal, A., and Valero, M., ShadowHTM: Using a dual-bitcell L1 Data Cache to Improve Hardware Transactional Memory Performance. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, 2010.
N. Miletić, Smiljkovic, V., Perfumo, C., Harris, T., Cristal, A., Hur, I., Unsal, O., and Valero, M., Transactification of a real-world system library, 5th ACM SIGPLAN Workshop on Transactional Computing - TRANSACT 2010. Paris, France, 2010.
P. Felber, Rivière, E., Moreira, W. M., Harmanci, D., Marlier, P., Diestelhorst, S., Hohmuth, M., Pohlack, M., Cristal, A., Hur, I., Unsal, O., Stenström, P., Dragojevic, A., Guerraoui, R., Kapalka, M., Gramoli, V., Drepper, U., Tomić, S., Afek, Y., Korland, G., Shavit, N., Fetzer, C., Nowack, M., and Riegel, T., The Velox Transactional Memory Stack, Micro, IEEE, vol. 30. pp. 76 -87, 2010.
2009
N. Markovic, González, R., Unsal, O., Valero, M., and Cristal, A., Architecture for Object-Oriented Programming Model. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, 2009.
F. Zyulkyarov, Gajinov, V., Unsal, O., Cristal, A., Ayguadé, E., Harris, T., and Valero, M., Atomic Quake: Using Transactional Memory in an Interactive Multiplayer Game Server, 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2009). ACM, Raleigh, North Carolina, United States, pp. 25–34, 2009.
S. Sanyal, Roy, S., Cristal, A., Unsal, O., and Valero, M., Clock gate on abort: Towards energy-efficient hardware Transactional Memory, 23rd IEEE International Symposium on Parallel {&} Distributed Processing (IPDPS 2009). IEEE, Rome, Italy, pp. 1–8, 2009.
S. Sanyal, Roy, S., Cristal, A., Unsal, O., and Valero, M., Dynamically Filtering Thread-Local Variables in Lazy-Lazy Hardware Transactional Memory, 11th IEEE International Conference on High Performance Computing and Communications, HPCC 2009. IEEE, Seoul, South Korea, pp. 171–179, 2009.
S. Tomić, Perfumo, C., Kulkarni, C., Armejach, A., Cristal, A., Unsal, O., Harris, T., and Valero, M., EazyHTM, Eager-Lazy Hardware Transactional Memory, 42nd International Symposium on Microarchitecture (MICRO). New York, United States, 2009.
N. Sönmez, Cristal, A., Unsal, O., Harris, T., and Valero, M., Profiling Transactional Memory applications on an Atomic Block Basis: A Haskell case study, Second Workshop on Programmability Issues for Multi-Core Computers (MULTIPROG 2009). Paphos, Cyprus, 2009.
V. Gajinov, Zyulkyarov, F., Unsal, O., Cristal, A., Ayguadé, E., Harris, T., and Valero, M., QuakeTM: parallelizing a complex sequential application using transactional memory, 23rd international conference on Supercomputing (ICS 2009). ACM, Yorktown Heights, NY, United States, pp. 126–135, 2009.
V. Gajinov, Zyulkyarov, F., Unsal, O. S., Cristal, A., Ayguadé, E., Harris, T., and Valero, M., QuakeTM: parallelizing a complex sequential application using transactional memory, Proceedings of the 23rd international conference on Supercomputing. ACM, pp. 126–135, 2009.
G. Kestor, Stipić, S., Unsal, O., Cristal, A., and Valero, M., RMS-TM: A Transactional Memory Benchmark for Recognition, Mining and Synthesis Applications, 4th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2009). Raleigh, NC, United States, 2009.
N. Sönmez, Perfumo, C., Stipić, S., Harris, T., Unsal, O., Cristal, A., and Valero, M., Software Transactional Memory Implementation, Advanced Computer Architecture and Computation for Embedded Systems (ACACES 2009). Academia Press, Terrassa, Spain, pp. 101–103, 2009.
N. Sönmez, Harris, T., Cristal, A., Unsal, O., and Valero, M., Taking the heat off transactions: Dynamic selection of pessimistic concurrency control, 23rd IEEE International Symposium on Parallel {&} Distributed Processing (IPDPS 2009). IEEE, Rome, Italy, pp. 1–10, 2009.
N. Sonmez, Harris, T., Cristal, A., Unsal, O., and Valero, M., Taking the heat off transactions: Dynamic selection of pessimistic concurrency control, Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing. IEEE Computer Society, Washington, DC, USA, pp. 1–10, 2009.
C. Kulkarni, Unsal, O., Cristal, A., Ayguadé, E., and Valero, M., Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions, 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2009). ACM, Raleigh, North Carolina, United States, pp. 307–308, 2009.
C. Kulkarni, Unsal, O., Cristal, A., Ayguadé, E., and Valero, M., Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions, ACM SIGPLAN Notices, vol. 44, pp. 307–308, 2009.
2008
I. González, Galluzzi, M., Veidenbaum, A., Ramírez, M. A., Cristal, A., and Valero, M., A distributed processor state management architecture for large-window processors, 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41). IEEE Computer Society, Lake Como, Italy, pp. 11–22, 2008.

Pages