Publications

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2008
González, I., Galluzzi, M., Veidenbaum, A., Ramírez, M.A., Cristal, A. & Valero, M. A distributed processor state management architecture for large-window processors. 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41) 11–22 (2008).at <http://capinfo.e.ac.upc.edu/PDFs/dir14/file003697.pdf>
González, I., Galluzzi, M., Veidenbaum, A., Ramirez, A., Cristal, A. & Valero, M. A distributed processor state management architecture for large-window processors. 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41) 11–22 (2008).at <http://capinfo.e.ac.upc.edu/PDFs/dir14/file003697.pdf>
González, I., Galluzzi, M., Veidenbaum, A., Ramírez, M.A., Cristal, A. & Valero, M. A Distributed Processor State Management Architecture for Large-Window Processors. (2008).
Vallejo, E., Harris, T., Cristal, A., Unsal, O. & Valero, M. Hybrid Transactional Memory to accelerate safe lock-based transactions. 3rd ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2008) (2008).at <http://capinfo.e.ac.upc.edu/PDFs/dir16/file003699.pdf>
Perfumo, C., Sönmez, N., Stipic, S., Unsal, O., Cristal, A., Harris, T. & Valero, M. The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment. Computing Frontiers '08 67–78 (2008).
Perfumo, C., Sönmez, N., Stipić, S., Unsal, O., Cristal, A., Harris, T. & Valero, M. The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment. 5th Conference on Computing Frontiers 67–78 (2008).at <http://capinfo.e.ac.upc.edu/PDFs/dir06/file003457.pdf>
Milovanovic, M., Ferrer, R., Gajinov, V., Unsal, O., Cristal, A., Ayguadé, E. & Valero, M. Nebelung: Execution Environment for Transactional OpenMP. International Journal of Parallel Programming 36, 326–346 (2008).
Vallejo, E., Sanyal, S., Harris, T., Vallejo, F., Beivide, R., Unsal, O., Cristal, A. & Valero, M. Towards Fair Scalable Locking. Workshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods (EPHAM 2008) (2008).at <http://capinfo.e.ac.upc.edu/PDFs/dir22/file003705.pdf>
Kestor, G., Unsal, O., Cristal, A. & Valero, M. Transactional Look-based Parallel Program. Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008 71–75 (2008).
Pericas, M., González, R., Cazorla, F., Cristal, A., Veidenbaum, A., Jiménez, D.A. & Valero, M. A two-level Load/Store Queue based on Execution Locality. (2008).
Pericàs, M., Cristal, A., Cazorla, F., González, R., Veidenbaum, A., Jiménez, D.A. & Valero, M. A Two-Level Load/Store Queue Based on Execution Locality. The 35th International Symposium on Computer Architecture (ISCA 2008) 25–36 (2008).at <http://capinfo.e.ac.upc.edu/PDFs/dir05/file003514.pdf>
Sönmez, N., Cristal, A., Unsal, O., Harris, T. & Valero, M. Why you should profile Transactional Memory Applications on an Atomic Block basis: A Haskell Case Study. (2008).
Zyulkyarov, F., Cristal, A., Cvijic, S., Ayguadé, E., Valero, M., Unsal, O. & Harris, T. WormBench: a configurable workload for evaluating transactional memory systems. 9th workshop on MEmory performance: DEaling with Applications, systems and architecture (MEDEA 2008) 61–68 (2008).at <http://capinfo.e.ac.upc.edu/PDFs/dir21/file003646.pdf>
2007
Milovanovic, M., Unsal, O., Cristal, A., Stipić, S., Zyulkyarov, F. & Valero, M. Compile time support for using transactional memory in C/C++ applications. The 11th Annual Workshop on the Interaction between Compilers and Computer Architecture (INTERACT-11) 16–23 (2007).at <http://capinfo.e.ac.upc.edu/PDFs/dir10/file003751.pdf>
Perfumo, C., Sönmez, N., Cristal, A., Unsal, O. & Valero, M. Development and Analysis of the Haskell Transactional Memory Benchmark Suite. 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07) 139–140 (2007).
Perfumo, C., Sönmez, N., Unsal, O., Cristal, A., Harris, T. & Valero, M. Dissecting Transactional Executions in Haskell. The Second ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2007) (2007).at <http://capinfo.e.ac.upc.edu/PDFs/dir17/file003700.pdf>
Lara, E., Cristal, A. & Valero, M. El Procesador Kilo-Ruanahead, una Alternativa para Reducir el Número de Registros Físicos del Procesador Kilo-Instruction. II Congreso Español de Informática (CEDI 2007) (2007).
Milovanovic, M., Unsal, O., Cristal, A., Stipić, S., Zyulkyarov, F. & Valero, M. Extending C/C++ Language with Atomic Constructs. II Congreso Español de Informática (CEDI 2007) (2007).
Pericàs, M., Cristal, A., Cazorla, F., González, R., Jiménez, D. & Valero, M. A Flexible Heterogeneous Multi-Core Architecture. The 2007 International Conference on Parallel Architectures and Compilation Techniques (PACT 2007) 13–24 (2007).at <http://capinfo.e.ac.upc.edu/PDFs/dir10/file003258.pdf>
Tomić, S., Cristal, A., Unsal, O. & Valero, M. Hardware Transactional Memory with Operating System Support, HTMOS. Workshop on Highly Parallel Processing on a Chip in conjunction with Euro-Par (2007).
Galluzzi, M., Vallejo, E., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J.E. & Valero, M. Implicit Transactional Memory in Kilo-Instruction Multiprocessor. The Twelfth Asia-Pacific Computer Systems Architecture Conference (ACSAC 2007) 339–353 (2007).
Sönmez, N., Perfumo, C., Stipić, S., Cristal, A., Unsal, O. & Valero, M. Increasing the Performance of Haskell Software Transactional Memory. II Congreso Español de Informática (CEDI 2007) (2007).
Zyulkyarov, F., Unsal, O., Cristal, A., Milovanovic, M., Ayguadé, E. & Valero, M. Memory Management for Transaction Processing Core in Heterogeneous Chip Multiprocessors. Workshop on Operating System Support for Heterogeneous Multicore Architectures (2007).
González, I., Galluzzi, M., Cristal, A. & Valero, M. The Multi-State Processor. 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07) 127–130 (2007).
González, I., Galluzzi, M., Cristal, A. & Valero, M. Multi-State Processor: Arquitectura sin ROB y con recuperaciones Precisas. II Congreso Español de Informática (CEDI 2007) (2007).
Milovanovic, M., Ferrer, R., Gajinov, V., Unsal, O., Cristal, A., Ayguadé, E. & Valero, M. Multithreaded software transactional memory and OpenMP. 8th MEDEA Workshop Memory Performance: Dealing With Applications, Systems And Architecture (MEDEA 2007) 81–88 (2007).at <http://capinfo.e.ac.upc.edu/PDFs/dir22/file003647.pdf>
García, A., Santana, O.J., Fernández, E., Medina, P., Cristal, A. & Valero, M. Reducing the Activity of Instruction Renaming in Loop Structures. II Congreso Español de Informática (CEDI 2007) (2007).
Zyulkyarov, F., Unsal, O., Cristal, A. & Valero, M. Synthetic Workloads for Transactional Memory. 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07) 135–137 (2007).
Harris, T., Cristal, A., Unsal, O., Ayguadé, E., Galiardi, F., Smith, B. & Valero, M. Transactional Memory: An Overview. IEEE Micro 27, 8–29 (2007).
Milovanovic, M., Ferrer, R., Unsal, O., Cristal, A., Martorell, X., Ayguadé, E., Labarta, J. & Valero, M. Transactional Memory and OpenMP. International Workshop on OpenMP (IWOMP-2007) 37–53 (2007).at <http://capinfo.e.ac.upc.edu/PDFs/dir05/file003195.pdf>
Sönmez, N., Perfumo, C., Stipić, S., Unsal, O., Cristal, A. & Valero, M. UnreadTVar: Extending Haskell Software Transactional Memory for Performance. The 8th Symposium on Trends in Functional Programming (TFP 2007) 1–11 (2007).at <http://capinfo.e.ac.upc.edu/PDFs/dir12/file003753.pdf>
2005
González, R., Cristal, A., Pericàs, M., Veidenbaum, A. & Valero, M. Arquitectura Simétrica Clusterizada basada en el Contenido. XVI Jornadas de Paralelismo (2005).
González, R., Cristal, A., Pericàs, M., Valero, M. & Veidenbaum, A. An asymetric Clustered Processor Based on Value Content. The 19th ACM International Conference on Supercomputing (ICS'05) 61–70 (2005).at <http://capinfo.e.ac.upc.edu/PDFs/dir24/file003040.pdf>
Pericàs, M., Cristal, A., González, R. & Valero, M. Decoupled State-Execute Architecture. 6th International Symposium on High Performance Computing (ISHPC-VI 2005) 68–78 (2005).at <http://capinfo.e.ac.upc.edu/PDFs/dir15/file003263.pdf>
Ramírez, T., Galluzzi, M., Cristal, A. & Valero, M. Different approaches using Kilo-instruction Processors. 2005 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-2005) (2005).at <http://capinfo.e.ac.upc.edu/PDFs/dir02/file003076.pdf>
Ramírez, T., Cristal, A., Pajuelo, A., Santana, O.J. & Valero, M. Eficacia vs. Eficiencia: Una decisión de diseño en Runahead. XVI Jornadas de Paralelismo (2005).at <http://capinfo.e.ac.upc.edu/PDFs/dir01/file003075.pdf>
Pericàs, M., Cristal, A., González, R., Jiménez, D.A. & Valero, M. Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor. 6th International Symposium on High Performance Computing (ISHPC-VI 2005) 56–67 (2005).at <http://capinfo.e.ac.upc.edu/PDFs/dir16/file003264.pdf>
Vallejo, E., Galluzzi, M., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J.E. & Valero, M. Implementing Kilo-Instruction Multiprocessors. International Conference on Pervasive Services (ICPS 2005) 325–336 (2005).
Cristal, A., Santana, O.J., Cazorla, F., Galluzzi, M., Ramírez, T., Pericàs, M. & Valero, M. Kilo-instruction Processors: Overcoming the Memory Wall. IEEE Micro 25, 48–57 (2005).
Vallejo, E., Galluzzi, M., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J.E. & Valero, M. KIMP: Multicheckpointing Multiprocessors. XVI Jornadas de Paralelismo (2005).

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