Publications

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2009
Sönmez, N. et al. Software Transactional Memory Implementation. Advanced Computer Architecture and Computation for Embedded Systems (ACACES 2009) 101–103 (Academia Press, 2009).
Sönmez, N., Harris, T., Cristal, A., Unsal, O. & Valero, M. Taking the heat off transactions: Dynamic selection of pessimistic concurrency control. 23rd IEEE International Symposium on Parallel {&} Distributed Processing (IPDPS 2009) 1–10 (IEEE, 2009).
Sonmez, N., Harris, T., Cristal, A., Unsal, O. & Valero, M. Taking the heat off transactions: Dynamic selection of pessimistic concurrency control. Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing 1–10 (2009). doi:10.1109/IPDPS.2009.5161032
Kulkarni, C., Unsal, O., Cristal, A., Ayguadé, E. & Valero, M. Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions. 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2009) 307–308 (ACM, 2009).
Kulkarni, C., Unsal, O., Cristal, A., Ayguadé, E. & Valero, M. Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions. ACM SIGPLAN Notices 44, 307–308 (2009).
2008
González, I. et al. A distributed processor state management architecture for large-window processors. 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41) 11–22 (IEEE Computer Society, 2008). at <http://capinfo.e.ac.upc.edu/PDFs/dir14/file003697.pdf>
González, I. et al. A Distributed Processor State Management Architecture for Large-Window Processors. (2008).
González, I. et al. A distributed processor state management architecture for large-window processors. 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41) 11–22 (IEEE Computer Society, 2008). at <http://capinfo.e.ac.upc.edu/PDFs/dir14/file003697.pdf>
Vallejo, E., Harris, T., Cristal, A., Unsal, O. & Valero, M. Hybrid Transactional Memory to accelerate safe lock-based transactions. 3rd ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2008) (2008). at <http://capinfo.e.ac.upc.edu/PDFs/dir16/file003699.pdf>
Perfumo, C. et al. The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment. 5th Conference on Computing Frontiers 67–78 (ACM, 2008). at <http://capinfo.e.ac.upc.edu/PDFs/dir06/file003457.pdf>
Perfumo, C. et al. The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment. Computing Frontiers '08 67–78 (2008).
Milovanovic, M. et al. Nebelung: Execution Environment for Transactional OpenMP. International Journal of Parallel Programming 36, 326–346 (2008).
Vallejo, E. et al. Towards Fair Scalable Locking. Workshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods (EPHAM 2008) (2008). at <http://capinfo.e.ac.upc.edu/PDFs/dir22/file003705.pdf>
Kestor, G., Unsal, O., Cristal, A. & Valero, M. Transactional Look-based Parallel Program. Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008 71–75 (HiPEAC Network of Excellence, 2008).
Pericàs, M. et al. A Two-Level Load/Store Queue Based on Execution Locality. The 35th International Symposium on Computer Architecture (ISCA 2008) 25–36 (The Institute of Electrical and Electronics Engineers, Inc., 2008). at <http://capinfo.e.ac.upc.edu/PDFs/dir05/file003514.pdf>
Pericas, M. et al. A two-level Load/Store Queue based on Execution Locality. (2008).
Sönmez, N., Cristal, A., Unsal, O., Harris, T. & Valero, M. Why you should profile Transactional Memory Applications on an Atomic Block basis: A Haskell Case Study. (2008).
Zyulkyarov, F. et al. WormBench: a configurable workload for evaluating transactional memory systems. 9th workshop on MEmory performance: DEaling with Applications, systems and architecture (MEDEA 2008) 61–68 (ACM, 2008). at <http://capinfo.e.ac.upc.edu/PDFs/dir21/file003646.pdf>
2007
Milovanovic, M. et al. Compile time support for using transactional memory in C/C++ applications. The 11th Annual Workshop on the Interaction between Compilers and Computer Architecture (INTERACT-11) 16–23 (2007). at <http://capinfo.e.ac.upc.edu/PDFs/dir10/file003751.pdf>
Perfumo, C., Sönmez, N., Cristal, A., Unsal, O. & Valero, M. Development and Analysis of the Haskell Transactional Memory Benchmark Suite. 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07) 139–140 (Academia Press, 2007).
Perfumo, C. et al. Dissecting Transactional Executions in Haskell. The Second ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2007) (2007). at <http://capinfo.e.ac.upc.edu/PDFs/dir17/file003700.pdf>
Lara, E., Cristal, A. & Valero, M. El Procesador Kilo-Ruanahead, una Alternativa para Reducir el Número de Registros Físicos del Procesador Kilo-Instruction. II Congreso Español de Informática (CEDI 2007) (2007).
Milovanovic, M. et al. Extending C/C++ Language with Atomic Constructs. II Congreso Español de Informática (CEDI 2007) (2007).
Pericàs, M. et al. A Flexible Heterogeneous Multi-Core Architecture. The 2007 International Conference on Parallel Architectures and Compilation Techniques (PACT 2007) 13–24 (2007). at <http://capinfo.e.ac.upc.edu/PDFs/dir10/file003258.pdf>
Tomić, S., Cristal, A., Unsal, O. & Valero, M. Hardware Transactional Memory with Operating System Support, HTMOS. Workshop on Highly Parallel Processing on a Chip in conjunction with Euro-Par (2007).
Galluzzi, M. et al. Implicit Transactional Memory in Kilo-Instruction Multiprocessor. The Twelfth Asia-Pacific Computer Systems Architecture Conference (ACSAC 2007) 339–353 (Springer, 2007).
Sönmez, N. et al. Increasing the Performance of Haskell Software Transactional Memory. II Congreso Español de Informática (CEDI 2007) (2007).
Zyulkyarov, F. et al. Memory Management for Transaction Processing Core in Heterogeneous Chip Multiprocessors. Workshop on Operating System Support for Heterogeneous Multicore Architectures (2007).
González, I., Galluzzi, M., Cristal, A. & Valero, M. The Multi-State Processor. 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07) 127–130 (Academia Press, 2007).
González, I., Galluzzi, M., Cristal, A. & Valero, M. Multi-State Processor: Arquitectura sin ROB y con recuperaciones Precisas. II Congreso Español de Informática (CEDI 2007) (2007).
Milovanovic, M. et al. Multithreaded software transactional memory and OpenMP. 8th MEDEA Workshop Memory Performance: Dealing With Applications, Systems And Architecture (MEDEA 2007) 81–88 (ACM, 2007). at <http://capinfo.e.ac.upc.edu/PDFs/dir22/file003647.pdf>
García, A. et al. Reducing the Activity of Instruction Renaming in Loop Structures. II Congreso Español de Informática (CEDI 2007) (2007).
Zyulkyarov, F., Unsal, O., Cristal, A. & Valero, M. Synthetic Workloads for Transactional Memory. 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07) 135–137 (Academia Press, 2007).
Harris, T. et al. Transactional Memory: An Overview. IEEE Micro 27, 8–29 (2007).
Milovanovic, M. et al. Transactional Memory and OpenMP. International Workshop on OpenMP (IWOMP-2007) 37–53 (Springer-Verlag, 2007). at <http://capinfo.e.ac.upc.edu/PDFs/dir05/file003195.pdf>
Sönmez, N. et al. UnreadTVar: Extending Haskell Software Transactional Memory for Performance. The 8th Symposium on Trends in Functional Programming (TFP 2007) 1–11 (2007). at <http://capinfo.e.ac.upc.edu/PDFs/dir12/file003753.pdf>
2006
Pericàs, M. et al. Boosting ILP{&}TLP with the Flexible Multi-Core (FMC). 2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06) 125–128 (Academia Press, 2006).
Vallejo, E. et al. Chip Multiprocessors with Implicit Transactions. 2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06) 167–170 (Academia Press, 2006).
Pericàs, M., Cristal, A., González, R., Jiménez, D. & Valero, M. A decoupled KILO-instruction processor. The 12th International Symposium on High-Performance Computer Architecture (HPCA-12) 53–64 (IEEE Press, 2006). at <http://capinfo.e.ac.upc.edu/PDFs/dir13/file003261.pdf>
Cristal, A. Kilo Instruction Processors. (2006).
Ramírez, T., Cristal, A., Santana, O. J., Pajuelo, A. & Valero, M. Kilo-Instruction Processors, RunAhead and Prefetch. ACM International Conference on Computing Frontiers (CF 2006) (ACM Press, 2006). at <http://capinfo.e.ac.upc.edu/PDFs/dir05/file003137.pdf>
2005
González, R., Cristal, A., Pericàs, M., Veidenbaum, A. & Valero, M. Arquitectura Simétrica Clusterizada basada en el Contenido. XVI Jornadas de Paralelismo (Thomson, 2005).
González, R., Cristal, A., Pericàs, M., Valero, M. & Veidenbaum, A. An asymetric Clustered Processor Based on Value Content. The 19th ACM International Conference on Supercomputing (ICS'05) 61–70 (ACM Press, 2005). at <http://capinfo.e.ac.upc.edu/PDFs/dir24/file003040.pdf>
Pericàs, M., Cristal, A., González, R. & Valero, M. Decoupled State-Execute Architecture. 6th International Symposium on High Performance Computing (ISHPC-VI 2005) 68–78 (Springer-Verlag, 2005). at <http://capinfo.e.ac.upc.edu/PDFs/dir15/file003263.pdf>
Ramírez, T., Galluzzi, M., Cristal, A. & Valero, M. Different approaches using Kilo-instruction Processors. 2005 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-2005) (Academia Press, 2005). at <http://capinfo.e.ac.upc.edu/PDFs/dir02/file003076.pdf>
Ramírez, T., Cristal, A., Pajuelo, A., Santana, O. J. & Valero, M. Eficacia vs. Eficiencia: Una decisión de diseño en Runahead. XVI Jornadas de Paralelismo (Thomson, 2005). at <http://capinfo.e.ac.upc.edu/PDFs/dir01/file003075.pdf>
Pericàs, M., Cristal, A., González, R., Jiménez, D. A. & Valero, M. Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor. 6th International Symposium on High Performance Computing (ISHPC-VI 2005) 56–67 (Springer-Verlag, 2005). at <http://capinfo.e.ac.upc.edu/PDFs/dir16/file003264.pdf>
Vallejo, E. et al. Implementing Kilo-Instruction Multiprocessors. International Conference on Pervasive Services (ICPS 2005) 325–336 (IEEE, 2005).
Cristal, A. et al. Kilo-instruction Processors: Overcoming the Memory Wall. IEEE Micro 25, 48–57 (2005).
Vallejo, E. et al. KIMP: Multicheckpointing Multiprocessors. XVI Jornadas de Paralelismo (Thomson, 2005).

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