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2013
F. Wartel, Kosmidis, L., Lo, C., Triquet, B., Quiñones, E., Abella, J., Gogonel, A., Baldovin, A., Mezzetti, E., Cucu-Grosjean, L., Vardanega, T., and Cazorla, F., Measurement-Based Probabilistic Timing Analysis: Lessons from an Integrated-Modular Avionics Case Study, 8th IEEE International Symposium on Industrial Embedded Systems (SIES). IEEE, Porto, Portugal, 2013.
L. Kosmidis, Vardanega, T., Quiñones, E., Abella, J., and Cazorla, F., Measurement-Based Probabilistic Timing Analysis to Buffer Resources, 13th International Workshop on Worst-Case Execution Time Analysis. OASIcs, Paris, France, pp. 2–10, 2013.
L. Kosmidis, Abella, J., Quiñones, E., and Cazorla, F., Multi-Level Unified Caches for Probabilistically Time Analysable Real-Time Systems, IEEE Real-Time Systems Symposium (RTSS) 2013. Vancouver, Canada, 2013.
S. Girbal, Moretó, M., Grasset, A., Abella, J., Quiñones, E., Cazorla, F., and Yehia, S., The Next Convergence: High-performance and Mission-critical Markets, Workshop on High-performance and Real-time Embedded Systems (HiRES). ––, Berlin, Germany, pp. 1–11, 2013.
M. Panic, Rodríguez, G., Quiñones, E., Abella, J., and Cazorla, F., On-Chip Ring Network Designs for Hard-Real Time Systems, 21st International Conference on Real-Time Networks and Systems. ACM, Sophia Antipolis, France, pp. 23–32, 2013.
T. Ungerer, Bradatsch, C., Gerdes, M., Kluge, F., Jahr, R., Mische, J., Fernandes, J., Zaykov, P., Zlatko, P., Boddeker, B., Kehr, S., Regler, H., Hugl, A., Rochange, C., Ozaktas, H., Cassé, H., Armelle, B., Sainrat, P., Lay, N., Broster, I., George, D., Panic, M., Quiñones, E., Cazorla, F., Abella, J., Uhrig, S., Rohde, M., and Pyka, A., parMERASA Multi-Core Execution of Parallelised Hard Real-Time Applications Supporting Analysability, Euromicro Conference on Digital System Design, DSD 2013. IEEE Computer Society, Santander, Spain, pp. 363–370, 2013.
Q. Liu, Jimenez, V., Moreto, M., Abella, J., and Cazorla, F., Per-task Energy Accounting in Computing Systems, In IEEE Computer Architecture Letters (CAL), vol. 13. pp. 1-6, 2013.
F. Cazorla, Quiñones, E., Vardanega, T., Cucu, L., Triquet, B., Bernat, G., Berger, E., Abella, J., Wartel, F., Houston, M., Santinelli, L., Kosmidis, L., Lo, C., and Maxim, D., PROARTIS: Probabilistically Analyzable Real-Time Systems, ACM Trans. Embed. Comput. Syst., vol. 12. ACM, New York, NY, USA, pp. 94:1–94:26, 2013.
L. Kosmidis, Curtsinger, C., Quiñones, E., Abella, J., Berger, E. D., and Cazorla, F., Probabilistic Timing Analysis on Conventional Cache Designs, ACM/IEEE Design, Automation, and Test in Europe (DATE). ACM, IEEE, Grenoble, France, pp. 603–606, 2013.
P. Radojkovic, Cakarevic, V., Verdu, J., Pajuelo, A., Cazorla, F., Nemirovsky, M., and Valero, M., Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors, IEEE Transactions on Parallel and Distributed Systems, vol. 24. IEEE Computer Society, Los Alamitos, CA, USA, pp. 2513-2525, 2013.
M. Paolieri, Quiñones, E., and Cazorla, F., Timing Effects of DDR Memory Systems in Hard Real-time Multicore Architectures: Issues and Solutions, ACM Trans. Embed. Comput. Syst., vol. 12. ACM, New York, NY, USA, pp. 64:1–64:26, 2013.
F. Cazorla, Vardanega, T., Quiñones, E., and Abella, J., Upper-bounding Program Execution Time with Extreme Value Theory., 13th International Workshop on Worst-Case Execution Time Analysis. OASIcs, Paris, France, pp. 61–70, 2013.
2012
M. Fernández, Gioiosa, R., Quiñones, E., Fossati, L., Zulianello, M., and Cazorla, F., Assessing the suitability of the NGMP multi-core processor in the Space domain, International Conference on Embedded Software (EMSOFT). 2012.
S. Manousopoulos, Moretó, M., Gioiosa, R., Koziris, N., and Cazorla, F., Characterizing Thread Placement in the IBM POWER7 Processor, IEEE International Symposium on Workload Characterization (IISWC-2013). IEEE, San Diego, United States, pp. 1–11, 2012.
C. Luque, Moretó, M., Cazorla, F., Gioiosa, R., Buyuktosunoglu, A., and Valero, M., CPU Accounting for Multicore Processors, IEEE Transactions on Computers, vol. 61. pp. 251–264, 2012.
P. Radojkovic, Girbal, S., Grasset, A., Quiñones, E., Yehia, S., and Cazorla, F., On the Evaluation of the Impact of Shared Resources in Multithreaded COTS Processors in Time-Critical Environments, ACM Transactions on Architecture and Code Optimization, vol. 8. 2012.
P. Radojkovic, Carpenter, P., Moreto, M., Ramirez, A., and Cazorla, F., Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem, International Symposium on Microarchitecture (MICRO-45). 2012.
V. Jiménez, Gioiosa, R., Cazorla, F., Buyuktosunoglu, A., Bose, P., and O'Connell, F. P., Making Data Prefetch Smarter: Adaptive Prefetching on POWER7, 21st International Conference on Parallel Architectures and Compilation Techniques (PACT-2012). ACM, Minneapolis, United States, pp. 137–146, 2012.
L. Cucu-Grosjean, Santinelli, L., Houston, M., Lo, C., Vardanega, T., Kosmidis, L., Abella, J., Mezzetti, E., Quiñones, E., and Cazorla, F., Measurement-Based Probabilistic Timing Analysis for Multi-path Programs, 24th Euromicro Conference on Real-Time Systems (ECRTS 2012). Robert Davis, Pisa, Italy, pp. 91–101, 2012.
P. Radojkovic, Girbal, S., Grasset, A., Quiñones, E., Cazorla, F., and Yehia, S., Multithreaded COTS Processors for Time-Critical Environments , Transactions on Architecture and Code Optimization (TACO). ACM, 2012.
P. Radojkovic, Cakarevic, V., Moretó, M., Verdú, J., Pajuelo, A., Cazorla, F., Nemirovsky, M., and Valero, M., Optimal Task Assignment in Multithreaded Processors: A Statistical Approach, 17th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-2012). London, United Kingdom, 2012.
P. Radojkovic, Cakarevic, V., Moreto, M., Verdu, J., Pajuelo, A., Cazorla, F., Nemirovsky, M., and Valero, M., Optimal Task Assignment in Multithreaded Processors: A Statistical Approach, Architectural Support for Programming Languages and Operating Systems (ASPLOS). ACM, 2012.
F. Cazorla, Quiñones, E., Vardanega, T., Cucu, L., Triquet, B., Bernat, G., Berger, E., Abella, J., Wartel, F., Houston, M., Santinelli, L., Kosmidis, L., Lo, C., and Maxim, D., PROARTIS: Probabilistically Analysable Real-Time Systems, Transactions on Embedded Computing Systems, no. Special Issue on Probabilistic Embedded Computing . ACM, 2012.
F. Cazorla, Quiñones, E., Vardanega, T., Cucu-Grosjean, L., Triquet, B., Berger, E. D., Abella, J., Wartel, F., Houston, M., Santinelli, L., Kosmidis, L., Lo, C., and Maxim, D., PROARTIS: Probabilistically Analysable Real-Time Systems, ACM Transactions on Embedded Computing Systems. 2012.
A. Morari, Boneti, C., Cazorla, F., Gioiosa, R., Cher, C. - Y., Buyuktosunoglu, A., Bose, P., and Valero, M., SMT Malleability in IBM POWER5 and POWER6 Processors, IEEE Transactions on Computers, vol. 00. 2012.
P. Radojkovic, Cakarevic, V., Verdú, J., Pajuelo, A., Cazorla, F., Nemirovsky, M., and Valero, M., Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors, IEEE Transactions on Parallel and Distributed Systems, vol. XX. 2012.
2011
V. Jimenez, Cazorla, F., Gioiosa, R., Kursun, E., Isci, C., Buyuktosunoglu, A., Bose, P., and Valero, M., A Case for Energy-Aware Accounting and Billing in Large-Scale Computing Facilities Cost Metrics and Design Implications., IEEE Micro. 2011.
V. Jimenez, Cazorla, F., Gioiosa, R., Valero, M., Boneti, C., Kursun, E., Cher, C., Isci, C., Buyuktosunoglu, A., and Bose, P., Characterizing Power and Temperature Behavior of POWER6-Based System, IEEE Journal of Emerging and Selected Topics in Circuits and Systems. 2011.
V. Jimenez, Gioiosa, R., Cazorla, F., Valero, M., Kursun, E., Isci, C., Buyuktosunoglu, A., and Bose, P., Energy-Aware Accounting and Billing in Large-Scale Computing Facilities, Micro, IEEE, vol. 31. pp. 60-71, 2011.
E. Quiñones, Abella, J., Cazorla, F., and Valero, M., Exploiting Intra-Task Slack Time of Load Operations for DVFS in Hard Real-Time Multi-core Systems, In Work in Progess (WiP), under the the 24nd Euromicro Conference on Real-Time Systems (ECRTS 2011). 2011.
B. Maric, Abella, J., Cazorla, F., and Valero, M., Hybrid High-Performance Low-Power and Ultra-Low Energy Reliable Caches, International Conference on Computing Frontiers (CF). pp. 12:1-12:2, 2011.
M. Paolieri, Quiñones, E., Cazorla, F., Davis, R. I., and Valero, M., IA3: An Interference Aware Allocation Algorithm for Multicore Hard Real-Time Systems. 17th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2011), 2011.
Q. Liu, Moretó, M., Abella, J., and Cazorla, F., Online Performance Prediction in Processors with DVFS Capabilities, ACACES 2011. Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. 2011.
A. Morari, Gioiosa, R., Wisniewski, R., Cazorla, F., and Valero, M., A Quantitative Analysis of OS Noise. Anchorage (Alaska) USA, 2011.
J. Abella, Quiñones, E., Cazorla, F., Sazeides, Y., and Valero, M., RVC: A Mechanism for Time-Analyzable Real-Time Processors with Faulty Caches. HiPEAC'11: 6th Int. Conference on High Performance and Embedded Architectures and Compilers, 2011.
J. Abella, Quiñones, E., Cazorla, F., Valero, M., and Sazeides, Y., RVC-based time-predictable faulty caches for safety-critical systems., IOLTS. IEEE, pp. 25-30, 2011.
M. Paolieri, Quiñones, E., Wolf, J., Petrov, Z., Cazorla, F., Uhrig, S., and Ungerer, T., A Software-Pipelined Approach to Multicore Execution of Timing Predictable Multi-Threaded Hard Real-Time Tasks. 14th IEEE International Symposium on Object/Component/Service-oriented Real-time Distributed Computing (ISORC 2011), 2011.
J. Abella, Cazorla, F., Quiñones, E., Grasset, A., Yehia, S., Bonnot, P., Gizopoulos, D., Mariani, R., and Bernat, G., Towards improved survivability in safety-critical systems, International On-Line Testing Symposium (IOLTS). pp. 240-245, 2011.
2010
K. Kedzierski, Moreto, M., Cazorla, F., and Valero, M., Adapting Cache Partitioning Algorithms to Real pseudo-LRU Replacement Policies. In 24th IEEE International Parallel & Distributed Processing Symposium (IPDPS), Atlanta, Georgia, 2010.
V. J. Jiménez, Cazorla, F., Gioiosa, R., Kursun, E., Isci, C., Buyuktosunoglu, A., and Valero, M., A Case for Energy Aware Accounting in Large Scale Computing Facilities: Cost Metrics and Implications for Processor Design. Workshop on Architectural Concerns in Large Datacenters (ACLD), in conjunction with ISCA, 2010.
M. Moreto, Cazorla, F., Ramirez, A., Sakellariou, R., and Valero, M., FlexDCP: a QoS framework for CMP architectures, ACM Operating Systems Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors, vol. 43, no. 2. pp. 86-96, 2010.
M. Moreto, Paolieri, M., Abella, J., Quiñones, E., Cazorla, F., and Valero, M., Hard Real-Time Capable Multicore Processors for Space Applications. ESTEC 1st Networking/Partnering Day, 2010.
C. Luque, Moreto, M., Cazorla, F., Gioiosa, R., and Valero, M., ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs. XXI Jornadas de Paralelismo, 2010.
M. Moreto, Cazorla, F., Sakellariou, R., and Valero, M., Load Balancing Using Dynamic Cache Allocation. ACM International Conference on Computing Frontiers (CF), 2010.
T. Ungerer, Cazorla, F., Sainrat, P., Bernat, G., Petrov, Z., Casse, H., Rochange, C., Quiñones, E., Uhrig, S., Gerdes, M., Guliashvili, I., Houston, M., Kluge, F., and Met, S., MERASA: Multi-Core Execution of Hard Real-Time Applications Supporting Analysability. IEEE Micro 2010, Special Issue on European Multicore Processing Projects, Vol. 30, No. 5, October 2010, 2010.
K. Kedzierski, Cazorla, F., Gioiosa, R., Buyuktosunoglu, A., and Valero, M., Power and Performance Aware Reconfigurable Cache for CMPs. Workshop on Next Generation Multicore/Manycore Technologies (IFMT), in conjunction with ISCA, 2010.
V. J. Jiménez, Boneti, C., Cazorla, F., Gioiosa, R., Kursun, E., Cher, C. - Y., Isci, C., Buyuktosunoglu, A., Bose, P., and Valero, M., Power and Thermal Characterization of POWER6 System. The 19th International Conference on Parallel Architectures and Compilation Techniques (PACT), 2010.
F. Cazorla, Pajuelo, A., Santana, O. J., Fernandez, E., and Valero, M., On the Problem of Evaluating the Performance of Multiprogrammed Workloads. , IEEE Transactions on Computers, vol. 59, no. 12. IEEE, 2010.
P. Radojkovic, Cakarevic, V., Verdú, J., Pajuelo, A., Cazorla, F., Nemirovsky, M., and Valero, M., Thread to Strand Binding of Parallel Network Applications in Massive Multi-Threaded Systems. In 15th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming, Bangalore, India, 2010.
V. J. Jiménez, Gioiosa, R., Kursun, E., Cazorla, F., Cher, C. - Y., Buyuktosunoglu, A., Bose, P., and Valero, M., Trends and techniques for energy efficient architectures. The 18th IEEE/IFIP VLSI System on Chip Conference (VLSI-SoC), 2010.

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