Publications

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2011
Kestor, G., Karakostas, V., Unsal, O., Cristal, A., Hur, I. & Valero, M. RMS-TM: A Comprehensive Benchmark Suite for Transactional Memory Systems. International Conference on Performance Engineering (ICPE 2011) (2011).
Abella, J., Quiñones, E., Cazorla, F., Sazeides, Y. & Valero, M. RVC: A Mechanism for Time-Analyzable Real-Time Processors with Faulty Caches. (2011).at <http://www.hipeac.net/conference>
Abella, J., Quiñones, E., Cazorla, F., Valero, M. & Sazeides, Y. RVC-based time-predictable faulty caches for safety-critical systems. IOLTS 25-30 (2011).at <http://dblp.uni-trier.de/db/conf/iolts/iolts2011.html#AbellaQCVS11>
Sánchez, F., Cabarcas, F., Ramirez, A. & Valero, M. Scalable multicore architectures for long DNA sequence comparison. Concurrency and Computation Practice and Experience 23, (2011).
González, J., Giménez, J., Casas, M., Moretó, M., Ramirez, A., Labarta, J. & Valero, M. Simulating Whole Supercomputer Applications. IEEE Micro 31, 32-45 (2011).
Subotic, V., Labarta, J. & Valero, M. Simulation environment to study overlapping of communication and computation. (2011).
Subotic, V., Sancho, J.C., Labarta, J. & Valero, M. A simulation framework to automatically analyze the communication-computation overlap in scientific applications. (2011).
Kestor, G., Gioiosa, R., Harris, T., Cristal, A., Unsal, O., Valero, M. & Hur, I. STM2: A Parallel STM for High Performance Simultaneous Multi-Threading Systems. The 20th IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT) (2011).
Yalcin, G., Unsal, O., Cristal, A., Hur, I. & Valero, M. SymptomTM: Symptom Based Error Detection and Recovery Using Hardware Transactional Memory. Parallel Architectures and Compilation Techniques (PACT) 199–200 (2011).
Sönmez, N., Arcas, O., Pflucker, O., Cristal, A., Unsal, O., Hur, I., Singh, S. & Valero, M. TMbox: A Flexible and Reconfigurable 16-core Hybrid Transactional Memory System. The 19th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2011) 1–8 (2011).
Sonmez, N., Arcas, O., Pflucker, O., Unsal, O., Cristal, A., Hur, I., Singh, S. & Valero, M. {TMbox}: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System. Proc. FCCM '11 146–153 (2011).
Sonmez, N., Arcas, O., Pflucker, O., Unsal, O., Cristal, A., Hur, I., Singh, S. & Valero, M. TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System. Proc. FCCM '11 146–153 (2011).
Rico, A., Duran, A., Cabarcas, F., Etsion, Y., Ramirez, A. & Valero, M. Trace-driven simulation of multithreaded applications. 2011 IEEE International Symposium on Performance Analysis of Systems and Software 87--96 (2011).
Hayes, T., Palomar, O., Unsal, O., Cristal, A. & Valero, M. True Vector Extensions for Decision Support DBMS Acceleration. (2011).
Armejach, A., Seyedi, A., Gil, R.T.J., Hur, I., Unsal, O., Cristal, A. & Valero, M. Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory. Parallel Architectures and Compilation Techniques (PACT) 360–370 (2011).
2010
Kedzierski, K., Moreto, M., Cazorla, F. & Valero, M. Adapting Cache Partitioning Algorithms to Real pseudo-LRU Replacement Policies. (2010).
Vallejo, E., Beivide, R., Cristal, A., Harris, T., Vallejo, F., Unsal, O. & Valero, M. Architectural Support for Fair Reader-Writer Locking. International Symposium on Microarchitecture (2010).
Torres, J., Ayguadé, E., Carrera, D., Guitart, J., Beltran, V., Becerra, Y., Badia, R.M., Labarta, J. & Valero, M. BSC contributions in Energy-aware Resource Management for Large Scale Distributed Systems. 1st Year Workshop of the COST Action IC0804 on Energy Efficiency in Large Scale Distributed Systems 76-79 (2010).
Etinski, M., Corbalán, J., Labarta, J. & Valero, M. BSLD Threshold Driven Power Management Policy for HPC Centers. (2010).
Jiménez, V.J., Cazorla, F., Gioiosa, R., Kursun, E., Isci, C., Buyuktosunoglu, A. & Valero, M. A Case for Energy Aware Accounting in Large Scale Computing Facilities: Cost Metrics and Implications for Processor Design. (2010).
Vega, A., Rico, A., Cabarcas, F., Ramirez, A. & Valero, M. Comparing last-level cache designs for CMP architectures. IFMT '10: International Forum on Next-Generation Multicore/Manycore Technologies (2010).
Zyulkyarov, F., Harris, T., Unsal, O., Cristal, A. & Valero, M. Debugging Programs that use Atomic Blocks and Transactional Memory. 15th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming (PPoPP 2010) (2010).
Gioiosa, R., McKee, S.A. & Valero, M. Designing OS for HPC Applications: Scheduling. (2010).
Marjanovic, V., Labarta, J., Ayguadé, E. & Valero, M. Effective Communication and Computation Overlap with Hybrid MPI/SMPSs. (2010).
Moreto, M., Cazorla, F., Ramirez, A., Sakellariou, R. & Valero, M. FlexDCP: a QoS framework for CMP architectures. ACM Operating Systems Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors 43, 86-96 (2010).
Moreto, M., Paolieri, M., Abella, J., Quiñones, E., Cazorla, F. & Valero, M. Hard Real-Time Capable Multicore Processors for Space Applications. (2010).
Luque, C., Moreto, M., Cazorla, F., Gioiosa, R. & Valero, M. ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs. (2010).
Paolieri, M., Bonesana, I., Gioiosa, R. & Valero, M. J-DSE: Joint Software and Hardware Design Space Exploration for Application Specific Processors. (2010).
Moreto, M., Cazorla, F., Sakellariou, R. & Valero, M. Load Balancing Using Dynamic Cache Allocation. (2010).
Sánchez, F., Cabarcas, F., Ramirez, A. & Valero, M. Long DNA Sequence Comparison on Multicore Architectures. 16th international Euro-Par conference on Parallel processing (2010).at <http://dx.doi.org/10.1007/978-3-642-15291-7_24>
Etinski, M., Corbalán, J., Labarta, J. & Valero, M. Optimizing Job Performance Under a Given Power Constraint In HPC Centers. (2010).
Marjanovic, V., Labarta, J., Ayguadé, E. & Valero, M. Overlapping Communication and Computation by Using a Hybrid MPI/SMPSs Approach. (2010).
Álvarez, M., Ramirez, A., Valero, M., Azevedo, A., Meenderinck, C. & Juurlink, B. Performance Evaluation of Macroblock-level Parallelization of H.264 Decoding on a cc-NUMA Multiprocessor Architecture. 4CCC. 4th Colombian Computing Conference, Bucaramanga (Colombia) (2010).
Kedzierski, K., Cazorla, F., Gioiosa, R., Buyuktosunoglu, A. & Valero, M. Power and Performance Aware Reconfigurable Cache for CMPs. (2010).
Jiménez, V.J., Boneti, C., Cazorla, F., Gioiosa, R., Kursun, E., Cher, C.-Y., Isci, C., Buyuktosunoglu, A., Bose, P. & Valero, M. Power and Thermal Characterization of POWER6 System. (2010).
Cazorla, F., Pajuelo, A., Santana, O.J., Fernandez, E. & Valero, M. On the Problem of Evaluating the Performance of Multiprogrammed Workloads. . IEEE Transactions on Computers 59, (2010).
Karakostas, V., Kestor, G., Unsal, O., Cristal, A., Hur, I. & Valero, M. RMS-TM: A challenging transactional memory benchmark suite. Advanced Computer Architecture and Computation for Embedded Systems (ACACES 2010) (2010).
Isaza, S., Sánchez, F., Gaydadjiev, G.N., Ramirez, A. & Valero, M. Scalability Analysis of Progressive Alignment in a Multicore. International Workshop on Multi-Core Computing Systems (MuCoCoS 2010) (2010).
Isaza, S., Sánchez, F., Gaydadjiev, G.N., Ramirez, A. & Valero, M. Scalability Analysis of Progressive Alignment on a Multicore. Fourth International Conference on Complex, Intelligent and Software Intensive Systems (CISIS '10) 889-894 (2010).at <http://dx.doi.org/10.1109/CISIS.2010.149>
Armejach, A., Seyedi, A., Gil, R.T.J., Hur, I., Unsal, O., Cristal, A. & Valero, M. ShadowHTM: Using a dual-bitcell L1 Data Cache to Improve Hardware Transactional Memory Performance. (2010).
Etsion, Y., Cabarcas, F., Rico, A., Ramirez, A., Badia, R.M., Ayguadé, E., Labarta, J. & Valero, M. Task Superscalar: An Out-of-Order Task Pipeline. IEEE/ACM Intl. Symp. on Microarchitecture (MICRO-43) 89-100 (2010).at <http://dx.doi.org/10.1109/MICRO.2010.13>
Etsion, Y., Ramirez, A., Badia, R.M., Ayguadé, E., Labarta, J. & Valero, M. Task Superscalar: Using Processors as Functional Units. USENIX Workshop on Hot Topics In Parallelism (HotPar) (2010).
Radojkovic, P., Cakarevic, V., Verdú, J., Pajuelo, A., Cazorla, F., Nemirovsky, M. & Valero, M. Thread to Strand Binding of Parallel Network Applications in Massive Multi-Threaded Systems. (2010).
Miletić, N., Smiljkovic, V., Perfumo, C., Harris, T., Cristal, A., Hur, I., Unsal, O. & Valero, M. Transactification of a real-world system library. 5th ACM SIGPLAN Workshop on Transactional Computing - TRANSACT 2010 (2010).
Jiménez, V.J., Gioiosa, R., Kursun, E., Cazorla, F., Cher, C.-Y., Buyuktosunoglu, A., Bose, P. & Valero, M. Trends and techniques for energy efficient architectures. (2010).
Boneti, C., Gioiosa, R., Cazorla, F. & Valero, M. Using hardware resource allocation to balance HPC applications, Parallel and Distributed Computing. (2010).
Etinski, M., Corbalán, J., Labarta, J. & Valero, M. Utilization Driven Power-Aware Job Scheduling. (2010).

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