Publications

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2011
M. Araya-Polo, Cabezas, J., Hanzich, M., Pericas, M., Morancho, E., Gelado, I., Shafiq, M., Rubio, F., Cela, J. M., Ayguadé, E., Navarro, N., and Valero, M., Assessing Accelerator-based HPC Reverse Time Migration, Transactions on Parallel and Distributed Systems, Special Issue on Accelerators, vol. 22(1). pp. 147-162, 2011.
V. Jimenez, Cazorla, F., Gioiosa, R., Kursun, E., Isci, C., Buyuktosunoglu, A., Bose, P., and Valero, M., A Case for Energy-Aware Accounting and Billing in Large-Scale Computing Facilities Cost Metrics and Design Implications., IEEE Micro. 2011.
V. Jimenez, Cazorla, F., Gioiosa, R., Valero, M., Boneti, C., Kursun, E., Cher, C., Isci, C., Buyuktosunoglu, A., and Bose, P., Characterizing Power and Temperature Behavior of POWER6-Based System. (invited paper), IEEE Journal of Emerging and Selected Topics in Circuits and Systems. 2011.
A. Seyedi, Armejach, A., Cristal, A., Unsal, O., Hur, I., and Valero, M., Circuit Design of a Dual-Versioning L1 Data Cache, Integration The VLSI Journal, 2011.
A. Seyedi, Armejach, A., Cristal, A., Unsal, O., Hur, I., and Valero, M., Circuit Design of a Dual-Versioning L1 Data Cache for Optimistic Concurrency, 21st Great Lakes Symposium on Very Large Scale Integration (GLSVLSI'11). Lausanne, Swaziland, 2011.
E. Akpinar, Tomić, S., Cristal, A., Unsal, O., and Valero, M., A Comprehensive Study of Conflict Resolution Policies in Hardware Transactional Memory, 6th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT). San Jose Convention Center, United States, 2011.
T. Ramírez, Santana, O. J., Pajuelo, A., and Valero, M., Efficient runahead threads. PACT 2010. International Conference on Parallel Architectures and Compiler Techniques, 2011.
E. Quiñones, Abella, J., Cazorla, F., and Valero, M., Exploiting Intra-Task Slack Time of Load Operations for DVFS in Hard Real-Time Multi-core Systems, In Work in Progess (WiP), under the the 24nd Euromicro Conference on Real-Time Systems (ECRTS 2011). 2011.
G. Yalcin, Unsal, O., Cristal, A., and Valero, M., FaulTM-multi: Fault Tolerance for Multithreaded Applications Running on Transactional Memory Hardware, Workshop on Wild and Sane Ideas in Speculation and Transactions. Galveston Island, TX, United States, 2011.
G. Yalcin, Unsal, O., Cristal, A., and Valero, M., FIMSIM: A fault injection infrastructure for microarchitectural simulators, 29th International Conference on Computer Design (ICCD). Amherst, MA, United States, pp. 431–432, 2011.
O. Arcas, Sönmez, N., Unsal, O., Cristal, A., and Valero, M., A Flexible Hybrid Transactional Memory Multicore on FPGA, Jornadas de Paralelismo 2011. Servicio de Publicaciones. Universidad de La Laguna, Tenerife, 2011, La Laguna, Tenerife, Spain, pp. 283–289, 2011.
N. Sönmez, Arcas, O., Sayilar, G., Cristal, A., Hur, I., Unsal, O., Singh, S., and Valero, M., From Plasma to BeeFarm: Design Experience of an FPGA-based Multicore Prototype, The 7th International Symposium on Applied Reconfigurable Computing (ARC 2011). Belfast, United Kingdom, pp. 1–10, 2011.
N. Sonmez, Arcas, O., Sayilar, G., Unsal, O., Cristal, A., Hur, I., Singh, S., and Valero, M., From Plasma to BeeFarm: Design Experience of an FPGA-based Multicore Prototype, ARC'11. 2011.
N. Sonmez, Arcas, O., Sayilar, G., Unsal, O., Cristal, A., Hur, I., Singh, S., and Valero, M., From plasma to beefarm: Design experience of an FPGA-based multicore prototype, Reconfigurable Computing: Architectures, Tools and Applications. Springer, pp. 350–362, 2011.
B. Maric, Abella, J., Cazorla, F., and Valero, M., Hybrid High-Performance Low-Power and Ultra-Low Energy Reliable Caches, International Conference on Computing Frontiers (CF). pp. 12:1-12:2, 2011.
M. Paolieri, Quiñones, E., Cazorla, F., Davis, R. I., and Valero, M., IA3: An Interference Aware Allocation Algorithm for Multicore Hard Real-Time Systems. 17th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2011), 2011.
V. Subotic, Sancho, J. C., Labarta, J., and Valero, M., The Impact of Application's Micro-Imbalance on the Communication-Computation Overlap, Parallel, Distributed and Network-Based Processing (PDP), 2011 19th Euromicro International Conference on. pp. 191-198, 2011.
V. Gajinov, Cristal, A., Milovanovic, M., Ayguadé, E., Unsal, O., and Valero, M., Integrating dataflow abstractions into transactional memory, Systems for Future Multi-Core Architectures (SFMA'11) . 2011.
V. Gajinov, Milovanovic, M., Unsal, O., Cristal, A., Ayguadé, E., and Valero, M., Integrating Dataflow Abstractions into Transactional Memory, First Workshop on Systems for Future Multi-Core Architectures (SFMA'11). Salzburg, Austria, pp. 1–6, 2011.
N. Markovic, Nemirovsky, D., González, R., Unsal, O., Valero, M., and Cristal, A., Object Oriented execution Model (OOM), New Directions in Computer Architecture (NDCA-2). San Jose, California, United States, 2011.
N. Markovic, Nemirovsky, D., González, R., Ünsal, O. S., Valero, M., and Cristal, A., Object Orienteed Execution Model (OOM), 2nd Workshop on New Directions in Computer Architecture (NDCA-2) Held in Conjunction with the 38th International Symposium on Computer Architecture (ISCA-38). San Jose, California, Sunday June 5th, 2011.
S. Isaza, Sánchez, F., Gaydadjiev, G. N., Ramirez, A., and Valero, M., Parameterizing Multicore Architectures for Multiple Sequence Alignment, 2011 International Conference on Computing Frontiers. 2011.
V. Subotic, Ferrer, R., Sancho, J. C., Labarta, J., and Valero, M., Quantifying the Potential Task-Based Dataflow Parallelism in MPI Applications, Euro-Par 2011 Parallel Processing, vol. 6852. Springer Berlin Heidelberg, pp. 39-51, 2011.
A. Morari, Gioiosa, R., Wisniewski, R., Cazorla, F., and Valero, M., A Quantitative Analysis of OS Noise. Anchorage (Alaska) USA, 2011.
S. Tomić, Cristal, A., Unsal, O., and Valero, M., Rapid Development of Error-Free Architectural Simulators using Dynamic Runtime Testing, 23rd International Symposium on Computer Architecture and High Performance Computing. Vitória, Espírito Santo, Brazil, 2011.
G. Kestor, Karakostas, V., Unsal, O., Cristal, A., Hur, I., and Valero, M., RMS-TM: A Comprehensive Benchmark Suite for Transactional Memory Systems, International Conference on Performance Engineering (ICPE 2011). ACM, Karlsruhe, Germany, 2011.
J. Abella, Quiñones, E., Cazorla, F., Sazeides, Y., and Valero, M., RVC: A Mechanism for Time-Analyzable Real-Time Processors with Faulty Caches. HiPEAC'11: 6th Int. Conference on High Performance and Embedded Architectures and Compilers, 2011.
J. Abella, Quiñones, E., Cazorla, F., Valero, M., and Sazeides, Y., RVC-based time-predictable faulty caches for safety-critical systems., IOLTS. IEEE, pp. 25-30, 2011.
F. Sánchez, Cabarcas, F., Ramirez, A., and Valero, M., Scalable multicore architectures for long DNA sequence comparison, Concurrency and Computation Practice and Experience, vol. 23, no. 17. 2011.
J. González, Giménez, J., Casas, M., Moretó, M., Ramirez, A., Labarta, J., and Valero, M., Simulating Whole Supercomputer Applications, IEEE Micro, vol. 31. IEEE, pp. 32-45, 2011.
V. Subotic, Labarta, J., and Valero, M., Simulation environment to study overlapping of communication and computation. IEEE International Symposium on Performance Analysis of Systems and Software, 2011.
V. Subotic, Sancho, J. C., Labarta, J., and Valero, M., A simulation framework to automatically analyze the communication-computation overlap in scientific applications. IEEE International Conference on Cluster Computing, 2011.
G. Kestor, Gioiosa, R., Harris, T., Cristal, A., Unsal, O., Valero, M., and Hur, I., STM2: A Parallel STM for High Performance Simultaneous Multi-Threading Systems, The 20th IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT). 2011.
G. Yalcin, Unsal, O., Cristal, A., Hur, I., and Valero, M., SymptomTM: Symptom Based Error Detection and Recovery Using Hardware Transactional Memory, Parallel Architectures and Compilation Techniques (PACT). Galveston Island, United States, pp. 199–200, 2011.
N. Sonmez, Arcas, O., Pflucker, O., Unsal, O., Cristal, A., Hur, I., Singh, S., and Valero, M., {TMbox}: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System, Proc. FCCM '11. pp. 146–153, 2011.
N. Sonmez, Arcas, O., Pflucker, O., Unsal, O., Cristal, A., Hur, I., Singh, S., and Valero, M., TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System, Proc. FCCM '11. pp. 146–153, 2011.
N. Sönmez, Arcas, O., Pflucker, O., Cristal, A., Unsal, O., Hur, I., Singh, S., and Valero, M., TMbox: A Flexible and Reconfigurable 16-core Hybrid Transactional Memory System, The 19th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2011). Salt Lake City, United States, pp. 1–8, 2011.
A. Rico, Duran, A., Cabarcas, F., Etsion, Y., Ramirez, A., and Valero, M., Trace-driven simulation of multithreaded applications, 2011 IEEE International Symposium on Performance Analysis of Systems and Software. p. 87--96, 2011.
T. Hayes, Palomar, O., Unsal, O., Cristal, A., and Valero, M., True Vector Extensions for Decision Support DBMS Acceleration. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, 2011.
A. Armejach, Seyedi, A., Gil, R. T. J., Hur, I., Unsal, O., Cristal, A., and Valero, M., Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory, Parallel Architectures and Compilation Techniques (PACT). Galveston Island, United States, pp. 360–370, 2011.
2010
K. Kedzierski, Moreto, M., Cazorla, F., and Valero, M., Adapting Cache Partitioning Algorithms to Real pseudo-LRU Replacement Policies. In 24th IEEE International Parallel & Distributed Processing Symposium (IPDPS), Atlanta, Georgia, 2010.
E. Vallejo, Beivide, R., Cristal, A., Harris, T., Vallejo, F., Unsal, O., and Valero, M., Architectural Support for Fair Reader-Writer Locking, in International Symposium on Microarchitecture, Atlanta, United States, 2010.
J. Torres, Ayguadé, E., Carrera, D., Guitart, J., Beltran, V., Becerra, Y., Badia, R. M., Labarta, J., and Valero, M., BSC contributions in Energy-aware Resource Management for Large Scale Distributed Systems, 1st Year Workshop of the COST Action IC0804 on Energy Efficiency in Large Scale Distributed Systems. pp. 76-79, 2010.
M. Etinski, Corbalán, J., Labarta, J., and Valero, M., BSLD Threshold Driven Power Management Policy for HPC Centers. IEEE International Symposium on Parallel&Distributed Processing, HPPAC workshop, 2010.
V. J. Jiménez, Cazorla, F., Gioiosa, R., Kursun, E., Isci, C., Buyuktosunoglu, A., and Valero, M., A Case for Energy Aware Accounting in Large Scale Computing Facilities: Cost Metrics and Implications for Processor Design.. Workshop on Architectural Concerns in Large Datacenters (ACLD), in conjunction with ISCA, 2010.

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