Publications

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2013
N. Rajovic, Carpenter, P., Gelado, I., Puzovic, N., Ramirez, A., and Valero, M., Supercomputing with commodity CPUs: are mobile SoCs ready for HPC?, SC13: International Conference for High Performance Computing, Networking, Storage and Analysis. Denver, United States, pp. 40–40, 2013.
M. Solinas, Badia, R. M., Bodin, F., Cohen, A., Evripidou, P., Faraboschi, P., Navarro, N., and Valero, M., The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices, Euromicro Conference on Digital System Design, DSD 2013. IEEE Computer Society, Santander, Spain, pp. 272–279, 2013.
P. Radojkovic, Cakarevic, V., Verdu, J., Pajuelo, A., Cazorla, F., Nemirovsky, M., and Valero, M., Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors, IEEE Transactions on Parallel and Distributed Systems, vol. 24. IEEE Computer Society, Los Alamitos, CA, USA, pp. 2513-2525, 2013.
V. Smiljkovic, Nowack, M., Miletic, N., Harris, T., Unsal, O., Cristal, A., and Valero, M., TM-dietlibc: A TM-aware Real-world System Library, The 27th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2013). IEEE, Boston, United States, 2013.
A. Rico, Ramirez, A., and Valero, M., Trace Filtering of Multithreaded Applications for CMP Memory Simulation, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2013). Austin, United States, pp. 134–135, 2013.
V. Smiljkovic, Stipić, S., Unsal, O., Cristal, A., and Valero, M., Transaction Coalescing - Lowering Transactional Overheads by Merging Transactions, Sixth Workshop on Programmability Issues for Heterogeneous Multicores (MULTIPROG-2013). Berlin, Germany, 2013.
2012
B. Maric, Abella, J., and Valero, M., ADAM: An Efficient Data Management Mechanism for Hybrid High and Ultra-Low Voltage Operation Caches, ACM/IEEE Great Lakes Symposium on VLSI. ACM New York, NY, USA ©2012, Salt Lake City, United States, pp. 245–250, 2012.
C. Luque, Moretó, M., Cazorla, F., Gioiosa, R., Buyuktosunoglu, A., and Valero, M., CPU Accounting for Multicore Processors, IEEE Transactions on Computers, vol. 61. pp. 251–264, 2012.
A. Morari, Gioiosa, R., Wisniewski, R. W., Rosenburg, B., Inglett, T., and Valero, M., Evaluating the impact of tlb misses on future HPC systems, The 26th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2012). IEEE, Shanghai, China, 2012.
G. Kestor, Gioiosa, R., Unsal, O., Cristal, A., and Valero, M., Hardware/Software Techniques for Assisted Execution Runtime Systems, The 2nd Workshop on Runtime Environments, Systems, Layering and Virtualized Environments (RESoLVE). 2012.
J. Labarta, Marjanovic, V., Ayguadé, E., Badia, R. M., and Valero, M., Hybrid Parallel Programming with MPI/StarSs, in Applications, Tools and Techniques on the Road to Exascale Computing, IOS Press, 2012.
E. Ayguadé, Badia, R. M., Bellens, P., Bueno-Hedo, J., Duran, A., Etsion, Y., Farreras, M., Ferrer, R., Labarta, J., Marjanovic, V., Martinell, L., Martorell, X., Pérez, J. M., Planas, J., Ramirez, A., Teruel, X., Tsalouchidou, I., and Valero, M., Hybrid/Heterogeneous Programming with OmpSs and its Software/Hardware Implications, in Programming Multi-Core and Many-Core Computing Systems (Wiley Series on Parallel and Distributed Computing) , Wiley Series on "Parallel and Distributed Computing"., John Wiley & Sons, Inc., 2012.
P. Radojkovic, Cakarevic, V., Moreto, M., Verdu, J., Pajuelo, A., Cazorla, F., Nemirovsky, M., and Valero, M., Optimal Task Assignment in Multithreaded Processors: A Statistical Approach, Architectural Support for Programming Languages and Operating Systems (ASPLOS). ACM, 2012.
P. Radojkovic, Cakarevic, V., Moretó, M., Verdú, J., Pajuelo, A., Cazorla, F., Nemirovsky, M., and Valero, M., Optimal Task Assignment in Multithreaded Processors: A Statistical Approach, 17th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-2012). London, United Kingdom, 2012.
A. Rico, Cabarcas, F., Villavieja, C., Pavlovic, M., Vega, A., Etsion, Y., Ramirez, A., and Valero, M., On the Simulation of Large-scale Architectures Using Multiple Application Abstraction Levels, ACM Transactions on Architecture and Code Optimization, vol. 8. p. 36, 2012.
A. Morari, Boneti, C., Cazorla, F., Gioiosa, R., Cher, C. - Y., Buyuktosunoglu, A., Bose, P., and Valero, M., SMT Malleability in IBM POWER5 and POWER6 Processors, IEEE Transactions on Computers, vol. 00. 2012.
S. Stipić, Tomić, S., Zyulkyarov, F., Cristal, A., Ünsal, O. S., and Valero, M., TagTM - accelerating STMs with hardware tags for fast meta-data access, DATE. pp. 39-44, 2012.
P. Radojkovic, Cakarevic, V., Verdú, J., Pajuelo, A., Cazorla, F., Nemirovsky, M., and Valero, M., Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors, IEEE Transactions on Parallel and Distributed Systems, vol. XX. 2012.
S. Tomić, Cristal, A., Unsal, O., and Valero, M., Using Dynamic Runtime Testing for Rapid Development of Architectural Simulators, International Journal of Parallel Programming. 2012.
T. Hayes, Palomar, O., Unsal, O., Cristal, A., and Valero, M., Vector Extensions for Decision Support DBMS Acceleration, The 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO45). pp. 166-176, 2012.
2011
M. Araya-Polo, Cabezas, J., Hanzich, M., Pericas, M., Morancho, E., Gelado, I., Shafiq, M., Rubio, F., Cela, J. M., Ayguadé, E., Navarro, N., and Valero, M., Assessing Accelerator-based HPC Reverse Time Migration, Transactions on Parallel and Distributed Systems, Special Issue on Accelerators, vol. 22(1). pp. 147-162, 2011.
V. Jimenez, Cazorla, F., Gioiosa, R., Kursun, E., Isci, C., Buyuktosunoglu, A., Bose, P., and Valero, M., A Case for Energy-Aware Accounting and Billing in Large-Scale Computing Facilities Cost Metrics and Design Implications., IEEE Micro. 2011.
V. Jimenez, Cazorla, F., Gioiosa, R., Valero, M., Boneti, C., Kursun, E., Cher, C., Isci, C., Buyuktosunoglu, A., and Bose, P., Characterizing Power and Temperature Behavior of POWER6-Based System, IEEE Journal of Emerging and Selected Topics in Circuits and Systems. 2011.
A. Seyedi, Armejach, A., Cristal, A., Unsal, O., Hur, I., and Valero, M., Circuit Design of a Dual-Versioning L1 Data Cache, Integration The VLSI Journal, 2011.
A. Seyedi, Armejach, A., Cristal, A., Unsal, O., Hur, I., and Valero, M., Circuit Design of a Dual-Versioning L1 Data Cache for Optimistic Concurrency, 21st Great Lakes Symposium on Very Large Scale Integration (GLSVLSI'11). Lausanne, Swaziland, 2011.
E. Akpinar, Tomić, S., Cristal, A., Unsal, O., and Valero, M., A Comprehensive Study of Conflict Resolution Policies in Hardware Transactional Memory, 6th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT). San Jose Convention Center, United States, 2011.
T. Ramírez, Santana, O. J., Pajuelo, A., and Valero, M., Efficient runahead threads. PACT 2010. International Conference on Parallel Architectures and Compiler Techniques, 2011.
V. Jimenez, Gioiosa, R., Cazorla, F., Valero, M., Kursun, E., Isci, C., Buyuktosunoglu, A., and Bose, P., Energy-Aware Accounting and Billing in Large-Scale Computing Facilities, Micro, IEEE, vol. 31. pp. 60-71, 2011.
E. Quiñones, Abella, J., Cazorla, F., and Valero, M., Exploiting Intra-Task Slack Time of Load Operations for DVFS in Hard Real-Time Multi-core Systems, In Work in Progess (WiP), under the the 24nd Euromicro Conference on Real-Time Systems (ECRTS 2011). 2011.
G. Yalcin, Unsal, O., Cristal, A., and Valero, M., FaulTM-multi: Fault Tolerance for Multithreaded Applications Running on Transactional Memory Hardware, Workshop on Wild and Sane Ideas in Speculation and Transactions. Galveston Island, TX, United States, 2011.
G. Yalcin, Unsal, O., Cristal, A., and Valero, M., FIMSIM: A fault injection infrastructure for microarchitectural simulators, 29th International Conference on Computer Design (ICCD). Amherst, MA, United States, pp. 431–432, 2011.
O. Arcas, Sönmez, N., Unsal, O., Cristal, A., and Valero, M., A Flexible Hybrid Transactional Memory Multicore on FPGA, Jornadas de Paralelismo 2011. Servicio de Publicaciones. Universidad de La Laguna, Tenerife, 2011, La Laguna, Tenerife, Spain, pp. 283–289, 2011.
N. Sönmez, Arcas, O., Sayilar, G., Cristal, A., Hur, I., Unsal, O., Singh, S., and Valero, M., From Plasma to BeeFarm: Design Experience of an FPGA-based Multicore Prototype, The 7th International Symposium on Applied Reconfigurable Computing (ARC 2011). Belfast, United Kingdom, pp. 1–10, 2011.
N. Sonmez, Arcas, O., Sayilar, G., Unsal, O., Cristal, A., Hur, I., Singh, S., and Valero, M., From Plasma to BeeFarm: Design Experience of an FPGA-based Multicore Prototype, ARC'11. 2011.
N. Sonmez, Arcas, O., Sayilar, G., Unsal, O., Cristal, A., Hur, I., Singh, S., and Valero, M., From plasma to beefarm: Design experience of an FPGA-based multicore prototype, Reconfigurable Computing: Architectures, Tools and Applications. Springer, pp. 350–362, 2011.
B. Maric, Abella, J., Cazorla, F., and Valero, M., Hybrid High-Performance Low-Power and Ultra-Low Energy Reliable Caches, International Conference on Computing Frontiers (CF). pp. 12:1-12:2, 2011.
M. Paolieri, Quiñones, E., Cazorla, F., Davis, R. I., and Valero, M., IA3: An Interference Aware Allocation Algorithm for Multicore Hard Real-Time Systems. 17th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2011), 2011.
V. Subotic, Sancho, J. C., Labarta, J., and Valero, M., The Impact of Application's Micro-Imbalance on the Communication-Computation Overlap, Parallel, Distributed and Network-Based Processing (PDP), 2011 19th Euromicro International Conference on. pp. 191-198, 2011.
V. Gajinov, Cristal, A., Milovanovic, M., Ayguadé, E., Unsal, O., and Valero, M., Integrating dataflow abstractions into transactional memory, Systems for Future Multi-Core Architectures (SFMA'11) . 2011.
V. Gajinov, Milovanovic, M., Unsal, O., Cristal, A., Ayguadé, E., and Valero, M., Integrating Dataflow Abstractions into Transactional Memory, First Workshop on Systems for Future Multi-Core Architectures (SFMA'11). Salzburg, Austria, pp. 1–6, 2011.
N. Markovic, Nemirovsky, D., González, R., Unsal, O., Valero, M., and Cristal, A., Object Oriented execution Model (OOM), New Directions in Computer Architecture (NDCA-2). San Jose, California, United States, 2011.
N. Markovic, Nemirovsky, D., González, R., Ünsal, O. S., Valero, M., and Cristal, A., Object Orienteed Execution Model (OOM), 2nd Workshop on New Directions in Computer Architecture (NDCA-2) Held in Conjunction with the 38th International Symposium on Computer Architecture (ISCA-38). San Jose, California, Sunday June 5th, 2011.
S. Isaza, Sánchez, F., Gaydadjiev, G. N., Ramirez, A., and Valero, M., Parameterizing Multicore Architectures for Multiple Sequence Alignment, 2011 International Conference on Computing Frontiers. 2011.
V. Subotic, Ferrer, R., Sancho, J. C., Labarta, J., and Valero, M., Quantifying the Potential Task-Based Dataflow Parallelism in MPI Applications, Euro-Par 2011 Parallel Processing, vol. 6852. Springer Berlin Heidelberg, pp. 39-51, 2011.
A. Morari, Gioiosa, R., Wisniewski, R., Cazorla, F., and Valero, M., A Quantitative Analysis of OS Noise. Anchorage (Alaska) USA, 2011.
S. Tomić, Cristal, A., Unsal, O., and Valero, M., Rapid Development of Error-Free Architectural Simulators using Dynamic Runtime Testing, 23rd International Symposium on Computer Architecture and High Performance Computing. Vitória, Espírito Santo, Brazil, 2011.
G. Kestor, Karakostas, V., Unsal, O., Cristal, A., Hur, I., and Valero, M., RMS-TM: A Comprehensive Benchmark Suite for Transactional Memory Systems, International Conference on Performance Engineering (ICPE 2011). ACM, Karlsruhe, Germany, 2011.
J. Abella, Quiñones, E., Cazorla, F., Sazeides, Y., and Valero, M., RVC: A Mechanism for Time-Analyzable Real-Time Processors with Faulty Caches. HiPEAC'11: 6th Int. Conference on High Performance and Embedded Architectures and Compilers, 2011.
J. Abella, Quiñones, E., Cazorla, F., Valero, M., and Sazeides, Y., RVC-based time-predictable faulty caches for safety-critical systems., IOLTS. IEEE, pp. 25-30, 2011.
F. Sánchez, Cabarcas, F., Ramirez, A., and Valero, M., Scalable multicore architectures for long DNA sequence comparison, Concurrency and Computation Practice and Experience, vol. 23, no. 17. 2011.

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