Publications

Export 173 results:
Author Title Type [ Year(Asc)]
Filters: Author is Francisco Cazorla  [Clear All Filters]
2006
K. Kedzierski, Cazorla, F., and Valero, M., Analysis of Simultaneous Multithreading Implementations in Current High-Performance Processors. ACACES 2006, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, 2006.
M. Pericàs, Cristal, A., González, R., Cazorla, F., Jiménez, D. A., and Valero, M., Boosting ILP{&}TLP with the Flexible Multi-Core (FMC), 2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06). Academia Press, L'Aquila, Italy, pp. 125–128, 2006.
C. Boneti, Cazorla, F., and Valero, M., Improving EDF for SMT processors. XVII Jornadas de Paralelismo, 2006.
J. Vera, Cazorla, F., Pajuelo, A., Santana, O. J., Fernández, E., and Valero, M., Looking for novel ways to obtain fair measurements in multithreaded architectures. XVII Jornadas de Paralelismo, 2006.
J. Vera, Cazorla, F., Pajuelo, A., Santana, O. J., Fernández, E., and Valero, M., A Novel Evaluation Methodology to Obtain Fair Measurements in Multithreaded Architectures. In Workshop on Modeling, Benchmarking and Simulation (MoBS)2006. Held in conjunction with ISCA, Boston, USA, 2006.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A., and Valero, M., Predictable Performance in SMT processors: Synergy Between the OS and SMTs, IEEE Transactions on Computers, vol. 55, no. 7. pp. 785-799, 2006.
2004
F. Cazorla, Fernández, E., Ramirez, A., and Valero, M., Approaching a Smart Sharing of Resources in SMT Processors, Workshop on Complexity-Effective Design (WCED). 2004.
F. Cazorla, Fernández, E., Ramirez, A., and Valero, M., DCache Warn: An I-Fetch Policy To Increase SMT Efficiency, 18th International Parallel and Distributed Processing Symposium (IPDPS-2004). IEEE Computer Society Press, 2004.
F. Cazorla, Ramirez, A., Valero, M., and Fernández, E., Dynamically Controlled Resource Allocation in SMT Processors, 37th Annual International Symposium on Microarchitecture (MICRO-37). pp. 171-182, 2004.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernandez, E., Ramirez, A., and Valero, M., Enabling SMT for Real-Time Embedded Systems., European Signal Processing Conference (EUSIPCO). 2004.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernandez, E., Ramirez, A., and Valero, M., Feasibility of QoS for SMT by Resource Allocation., Lecture Notes in Computer Science (LNCS) , vol. 3149/2004. 2004.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A., and Valero, M., Implicit vs. Explicit Resource Allocation in SMT Processors, 2004 Euromicro Symposium on Digital Systems Design (DSD 2004). Rennes, France, pp. 44-51, 2004.
F. Cazorla, Fernández, E., Ramirez, A., and Valero, M., Optimizing Long-Latency-Load-Aware Fetch Policies for SMT Processors, International Journal of High Performance Computing and Networking (IJHPCN), vol. 2, no. 2. 2004.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A., and Valero, M., Predictable Performance in SMT Processors, Computing Frontiers (CF'04). 2004.
F. Cazorla, Ramirez, A., Valero, M., Knijnenburg, P., Sakellariou, R., and Fernández, E., QoS for High-Performance SMT Processors in Embedded Systems, IEEE Micro, vol. 24. pp. 24-31, 2004.
E. Fernández, Cazorla, F., Ramirez, A., Knijnenburg, P., Sakellariou, R., and Valero, M., Throughput versus Quality of Service in SMT processors, Euromicro-DSD (Digital System Design). Euromicro-DSD (Digital System Design), 2004.
2003
F. Cazorla, Fernández, E., Ramirez, A., and Valero, M., Improving Memory Latency Aware Fetch Policies for SMT Processors, 5th International Symposium on High Performance Computing (ISHPC-V). Springer-Verlag, Tokyo, Japan, pp. 70-85, 2003.

Pages