Publications

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2004
F. Cazorla, Fernández, E., Ramirez, A., and Valero, M., DCache Warn: An I-Fetch Policy To Increase SMT Efficiency, 18th International Parallel and Distributed Processing Symposium (IPDPS-2004). IEEE Computer Society Press, 2004.
F. Cazorla, Ramirez, A., Valero, M., and Fernández, E., Dynamically Controlled Resource Allocation in SMT Processors, 37th Annual International Symposium on Microarchitecture (MICRO-37). pp. 171-182, 2004.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernandez, E., Ramirez, A., and Valero, M., Enabling SMT for Real-Time Embedded Systems., European Signal Processing Conference (EUSIPCO). 2004.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernandez, E., Ramirez, A., and Valero, M., Feasibility of QoS for SMT by Resource Allocation., Lecture Notes in Computer Science (LNCS) , vol. 3149/2004. 2004.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A., and Valero, M., Implicit vs. Explicit Resource Allocation in SMT Processors, 2004 Euromicro Symposium on Digital Systems Design (DSD 2004). Rennes, France, pp. 44-51, 2004.
F. Cazorla, Fernández, E., Ramirez, A., and Valero, M., Optimizing Long-Latency-Load-Aware Fetch Policies for SMT Processors, International Journal of High Performance Computing and Networking (IJHPCN), vol. 2, no. 2. 2004.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A., and Valero, M., Predictable Performance in SMT Processors, Computing Frontiers (CF'04). 2004.
F. Cazorla, Ramirez, A., Valero, M., Knijnenburg, P., Sakellariou, R., and Fernández, E., QoS for High-Performance SMT Processors in Embedded Systems, IEEE Micro, vol. 24. pp. 24-31, 2004.
E. Fernández, Cazorla, F., Ramirez, A., Knijnenburg, P., Sakellariou, R., and Valero, M., Throughput versus Quality of Service in SMT processors, Euromicro-DSD (Digital System Design). Euromicro-DSD (Digital System Design), 2004.
2003
F. Cazorla, Fernández, E., Ramirez, A., and Valero, M., Improving Memory Latency Aware Fetch Policies for SMT Processors, 5th International Symposium on High Performance Computing (ISHPC-V). Springer-Verlag, Tokyo, Japan, pp. 70-85, 2003.

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