Publications

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2010
Vallejo, E., Beivide, R., Cristal, A., Harris, T., Vallejo, F., Unsal, O. & Valero, M. Architectural Support for Fair Reader-Writer Locking. International Symposium on Microarchitecture (2010).
2008
Vallejo, E., Harris, T., Cristal, A., Unsal, O. & Valero, M. Hybrid Transactional Memory to accelerate safe lock-based transactions. 3rd ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2008) (2008).at <http://capinfo.e.ac.upc.edu/PDFs/dir16/file003699.pdf>
Vallejo, E., Sanyal, S., Harris, T., Vallejo, F., Beivide, R., Unsal, O., Cristal, A. & Valero, M. Towards Fair Scalable Locking. Workshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods (EPHAM 2008) (2008).at <http://capinfo.e.ac.upc.edu/PDFs/dir22/file003705.pdf>
2007
Galluzzi, M., Vallejo, E., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J.E. & Valero, M. Implicit Transactional Memory in Kilo-Instruction Multiprocessor. The Twelfth Asia-Pacific Computer Systems Architecture Conference (ACSAC 2007) 339–353 (2007).
2006
Vallejo, E., Galluzzi, M., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J.E. & Valero, M. Chip Multiprocessors with Implicit Transactions. 2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06) 167–170 (2006).
2005
Moreto, M., Martínez, C., Beivide, R., Vallejo, E. & Valero, M. Hierarchical Gaussian Topologies. (2005).
Moreto, M., Martínez, C., Vallejo, E., Beivide, M. & Valero, M. Hierarchical Topologies for Large-Scale Two-Level Networks. (2005).
Vallejo, E., Galluzzi, M., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J.E. & Valero, M. Implementing Kilo-Instruction Multiprocessors. International Conference on Pervasive Services (ICPS 2005) 325–336 (2005).
Vallejo, E., Galluzzi, M., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J.E. & Valero, M. KIMP: Multicheckpointing Multiprocessors. XVI Jornadas de Paralelismo (2005).