Publications

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Author Title Type [ Year(Asc)]
Filters: Author is Carmelo Acosta  [Clear All Filters]
2009
C. Acosta, Cazorla, F., Ramirez, A., and Valero, M., Thread to Core Assignment in SMT On-Chip Multiprocessors, 21st International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'09). 2009.
2007
C. Acosta, Cazorla, F., Ramirez, A., and Valero, M., Core to Memory Interconnection Implications for Forthcoming On-Chip Multiprocessors, 1st Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI 2007). 2007.
2005
C. Acosta, Falcón, A., Ramirez, A., and Valero, M., A Complexity-Effective Simultaneous Multithreading Architecture, 34th International Conference on Parallel Processing (ICPP 2005). 2005.
C. Acosta, Falcón, A., Ramirez, A., and Valero, M., Complexity-Effectiveness in Multithreading Architectures, In 2005 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-2005). L'Aquila (Italy), pp. 79-82, 2005.
C. Acosta, Falcón, A., Ramirez, A., and Valero, M., hdSMT: An Heterogeneity-Aware Simultaneous Multithreaded Architecture, XVI Jornadas de Paralelismo. pp. 59-66, 2005.