Publications

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2009
Acosta, C., Cazorla, F., Ramirez, A. & Valero, M. Thread to Core Assignment in SMT On-Chip Multiprocessors. 21st International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'09) (2009).
2008
Acosta, C., Cazorla, F., Ramirez, A. & Valero, M. MFLUSH: Handling Long-latency loads in SMT On-Chip Multiprocessors. International Conference on Parallel Processing (ICPP) 173-181 (2008).
2007
Acosta, C., Cazorla, F., Ramirez, A. & Valero, M. Core to Memory Interconnection Implications for Forthcoming On-Chip Multiprocessors. 1st Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI 2007) (2007).
2005
Acosta, C., Falcón, A., Ramirez, A. & Valero, M. A Complexity-Effective Simultaneous Multithreading Architecture. 34th International Conference on Parallel Processing (ICPP 2005) (2005).
Acosta, C., Falcón, A., Ramirez, A. & Valero, M. Complexity-Effectiveness in Multithreading Architectures. In 2005 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-2005) 79-82 (2005).
Acosta, C., Falcón, A., Ramirez, A. & Valero, M. hdSMT: An Heterogeneity-Aware Simultaneous Multithreaded Architecture. XVI Jornadas de Paralelismo 59-66 (2005).
2004
Acosta, C., Falcón, A., Ramirez, A. & Valero, M. Heterogeneity-Aware Architectures. XV Jornadas de Paralelismo 202-207 (2004).
Galluzzi, M., Puente, V., Santana, O.J., Acosta, C., Cristal, A., Beivide, R., Monasterio, J.A.G. & Valero, M. Introducing Kilo-instruction Multiprocessors. XV Jornadas de Paralelismo (2004).at <http://capinfo.e.ac.upc.edu/PDFs/dir19/file002977.pdf>
2003
Acosta, C., Vajapeyam, S., Ramirez, A. & Valero, M. CDE: A Compiler-driven, Dependence-Centric, Eager-executing Architecture for the Billion Transistors Era. Workshop on Complexity-Effective Design (WCED 2003) (2003).
Acosta, C., Galluzzi, M., Vajapeyam, S., Ramirez, A. & Valero, M. Dealing with Billions of Transistors. XIV Jornadas de Paralelismo 547-552 (2003).