Publications

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2004
Cazorla, F., Knijnenburg, P., Sakellariou, R., Fernandez, E., Ramirez, A. & Valero, M. Enabling SMT for Real-Time Embedded Systems. European Signal Processing Conference (EUSIPCO) (2004).
Cazorla, F., Knijnenburg, P., Sakellariou, R., Fernandez, E., Ramirez, A. & Valero, M. Feasibility of QoS for SMT by Resource Allocation. Lecture Notes in Computer Science (LNCS) 3149/2004, (2004).
Acosta, C., Falcón, A., Ramirez, A. & Valero, M. Heterogeneity-Aware Architectures. XV Jornadas de Paralelismo 202-207 (2004).
Cazorla, F., Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A. & Valero, M. Implicit vs. Explicit Resource Allocation in SMT Processors. 2004 Euromicro Symposium on Digital Systems Design (DSD 2004) 44-51 (2004).
Falcón, A., Santana, O.J., Ramirez, A. & Valero, M. A latency conscious SMT branch predictor architecture. International Journal of High Performance Computing and Networking (IJHPCN) 2, 11-21 (2004).
Valero, M., Santana, O.J., Ramirez, A. & Larriba-Pey, J.L. A Low Complexity Fetch Architecture for High Performance Superscalar Processors. ACM Transactions on Architecture and Compiler Optimizations (TACO) 1, 220-245 (2004).
Santana, O.J., Ramirez, A., Larriba-Pey, J.L. & Valero, M. A Low-Complexity Fetch Architecture for High-Performance Superscalar Processors. ACM Transactions on Architecture and Code Optimization 1, 220-245 (2004).
Falcón, A., Ramirez, A. & Valero, M. A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors. 10th International Conference on High Performance Computer Architecture (HPCA-10) 244-253 (2004).
Cazorla, F., Fernández, E., Ramirez, A. & Valero, M. Optimizing Long-Latency-Load-Aware Fetch Policies for SMT Processors. International Journal of High Performance Computing and Networking (IJHPCN) 2, (2004).
Cazorla, F., Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A. & Valero, M. Predictable Performance in SMT Processors. Computing Frontiers (CF'04) (2004).
Falcón, A., Stark, J., Ramirez, A., Lai, K. & Valero, M. Prophet/Critic Hybrid Branch Prediction. 31st Annual International Symposium on Computer Architecture (ISCA-31) 250-262 (2004).
Cazorla, F., Ramirez, A., Valero, M., Knijnenburg, P., Sakellariou, R. & Fernández, E. QoS for High-Performance SMT Processors in Embedded Systems. IEEE Micro 24, 24-31 (2004).
Santana, O.J., Ramirez, A. & Valero, M. Reducing Fetch Architecture Complexity Using Procedure Inlining. 8th Workshop on Interaction between Compilers and Computer Architectures (INTERACT) (2004).
Álvarez, M., Sánchez, F., Salami, E., Ramirez, A. & Valero, M. Scalability and Complexity of 2-Dimensional SIMD Extensions. XV Jornadas de Paralelismo 190-195 (2004).
Falcón, A., Santana, O.J., Ramirez, A. & Valero, M. Selecting Where to Simulate SPEC2000 Using Streams Analysis. XV Jornadas de Paralelismo 208--213 (2004).
Santana, O.J., Falcón, A., Ramirez, A. & Valero, M. Stream Predictor Guided Instruction Decoding. XV Jornadas de Paralelismo 184-189 (2004).
Fernández, E., Cazorla, F., Ramirez, A., Knijnenburg, P., Sakellariou, R. & Valero, M. Throughput versus Quality of Service in SMT processors. Euromicro-DSD (Digital System Design) (2004).
2003
Santana, O.J., Galluzzi, M., Ramirez, A. & Valero, M. An Analysis of Dynamic Instruction Streams. XIV Jornadas de Paralelismo 527-532 (2003).
Acosta, C., Vajapeyam, S., Ramirez, A. & Valero, M. CDE: A Compiler-driven, Dependence-Centric, Eager-executing Architecture for the Billion Transistors Era. Workshop on Complexity-Effective Design (WCED 2003) (2003).
Acosta, C., Galluzzi, M., Vajapeyam, S., Ramirez, A. & Valero, M. Dealing with Billions of Transistors. XIV Jornadas de Paralelismo 547-552 (2003).
Cazorla, F., Fernández, E., Ramirez, A. & Valero, M. Improving Memory Latency Aware Fetch Policies for SMT Processors. 5th International Symposium on High Performance Computing (ISHPC-V) 70-85 (2003).at <http://personals.ac.upc.edu/fcazorla/articles/fcazorla_ishpc2003.pdf>
Santana, O.J., Ramirez, A. & Valero, M. Latency Tolerant Branch Predictors. 2003 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'03) 30-39 (2003).
Falcón, A., Santana, O.J., Ramirez, A. & Valero, M. Tolerating branch predictor latency on SMT. 5th International Symposium on High Performance Computing (ISHPC-V) 86-98 (2003).
2002
García, A., Fernández, E., Medina, P., Ramirez, A. & Valero, M. Analisis y caracterización de los bucles. XIII Jornadas de Paralelismo (2002).
Knijnenburg, P., Ramirez, A., Larriba-Pey, J.L. & Valero, M. Branch classification for SMT fetch gating. 6th Workshop on Multithreaded Execution, Architecture and Compilation (MTEAC6) (2002).
Knijnenburg, P., Ramirez, A., Latorre, F., Larriba-Pey, J.L. & Valero, M. Branch Classification to Control Instruction Fetch in Simultaneous Multithreaded Architectures. International Workshop on Innovative Architecture (IWIA 2002) 67-76 (2002).
Vandierendonck, H., Ramirez, A., Bosschere, K.D. & Valero, M. A comparative study of redundancy in trace caches. Intl. Euro-Par Conference 512-516 (2002).
Santana, O.J., Falcón, A., Fernández, E., Medina, P., Ramirez, A. & Valero, M. A Comprehensive Analysis of Indirect Branch Prediction. 4th International Symposium on High Performance Computing (ISHPC-4) 133-141 (2002).
Cazorla, F., Medina, P., Fernández, E., Ramirez, A. & Valero, M. Estudio y evaluación de mecanismos de control de la Especulación. In XIII Jornadas de Paralelismo, Lleida (Spain) (2002).
Ramirez, A., Santana, O.J., Larriba-Pey, J.L. & Valero, M. Fetching Instruction Streams. 35th Annual International Symposium on Microarchitecture (MICRO-35) 371-382 (2002).
Eng, M., Wang, H., Wang, P., Ramirez, A., Fung, J. & Shen, J. Mesocode: Optimizations for Improving Fetch Bandwidth of Itanium Processors. Workshop on Complexity-Effective Design (2002).
Ramirez, A., Larriba-Pey, J.L., Navarro, C., Valero, M. & Torrellas, J. Software Trace Cache for Commercial Applications. International Journal of Parallel Programming 30, 373-395 (2002).
Falcón, A., Santana, O.J., Medina, P., Fernández, E., Ramirez, A. & Valero, M. Studying New Ways for Improving Adaptive History Length Branch Predictors. 4th International Symposium on High Performance Computing (ISHPC-4) 271-279 (2002).
2001
Falcón, A., Santana, O.J., Medina, P., Fernández, E., Ramirez, A. & Valero, M. An Analysis of Dynamic History Length Fitting. XII Jornadas de Paralelismo, Valencia (Spain) (2001).
Ramirez, A., Larriba-Pey, J.L. & Valero, M. Branch Prediction Using Profile Data. 7th International Euro-Par Conference (Euro-Par'2001) 386-393 (2001).
Ramirez, A., Barroso, L.A., Gharachorloo, K., Cohn, R., Larriba-Pey, J.L., Lowney, G. & Valero, M. Code Layout Optimizations for Transaction Processing Workloads. 28th Annual International Symposium on Computer Architecture (ISCA-28) 155-164 (2001).
Santana, O.J., Falcón, A., Fernández, E., Medina, P., Ramirez, A. & Valero, M. An In-Depth Evaluation of the Multi-Stage Cascaded Predictor. XII Jornadas de Paralelismo, Valencia (Spain) (2001).
Ramirez, A., Larriba-Pey, J.L. & Valero, M. Instruction Fetch Architectures and Code Layout Optimizations. Proceedings of the IEEE 89, 1588-1609 (2001).
2000
Ramirez, A., Larriba-Pey, J.L. & Valero, M. The Effect of Code Reordering on Branch Prediction. International Conference on Parallel Architectures and Compilation Techniques (PACT 2000) 189-198 (2000).
Navarro, C., Ramirez, A., Larriba-Pey, J.L. & Valero, M. Fetch Engines and Databases. 3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3) (2000).
Navarro, C., Ramirez, A., Larriba-Pey, J.L. & Valero, M. On the Performance of Fetch Engines Running DSS Workloads. 6th International Euro-Par Conference (EuroPar'2000) 591-595 (2000).
Ramirez, A., Larriba-Pey, J.L. & Valero, M. Semi-static Branch Prediction for Optimized Code Layouts. 3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3) (2000).
Ramirez, A., Larriba-Pey, J.L. & Valero, M. A Stream Processor Front-end. IEEE Technical Committee on Computer Architecture Newsletter 10-13 (2000).
Ramirez, A., Larriba-Pey, J.L. & Valero, M. Trace Cache Redundancy: Red & Blue Traces. Sixth International Symposium on High-Performance Computer Architecture (HPCA'2000) 325-333 (2000).
1999
Ramirez, A., Larriba-Pey, J.L., Navarro, C., Serrano, X., Torrellas, J. & Valero, M. Optimization of Instruction Fetch for Decision Support Workloads. International Conference on Parallel Processing 238-245 (1999).
Ramirez, A., Larriba-Pey, J.L., Navarro, C., Serrano, X., Torrellas, J. & Valero, M. Optimizing Instruction Fetch for Decision Support Workloads. 2nd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-2) (1999).
Ramirez, A., Larriba-Pey, J.L., Navarro, C., Torrellas, J. & Valero, M. Software Trace Cache. International Conference on Supercomputing (ICS'1999) 119-126 (1999).
Ramirez, A., Larriba-Pey, J.L., Navarro, C., Serrano, X., Torrellas, J. & Valero, M. Trace Cache Redundancy. X Jornadas de Paralelismo 39-44 (1999).

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