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F. Cazorla, Fernández, E., Ramirez, A., and Valero, M., Improving Memory Latency Aware Fetch Policies for SMT Processors, 5th International Symposium on High Performance Computing (ISHPC-V). Springer-Verlag, Tokyo, Japan, pp. 70-85, 2003.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A., and Valero, M., Implicit vs. Explicit Resource Allocation in SMT Processors, 2004 Euromicro Symposium on Digital Systems Design (DSD 2004). Rennes, France, pp. 44-51, 2004.
C. Luque, Moreto, M., Cazorla, F., Gioiosa, R., Buyuktosunoglu, A., and Valero, M., ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs. In International Symposium on Parallel Architectures and Compilation Techniques, North Carolina, USA, 2009.
M. Panic, Hernandez, C., Abella, J., Perez, A. Roca, Quiñones, E., and Cazorla, F., Improving Performance Guarantees in Wormhole Mesh NoC Designs, In Proceedings of the Design Automation and Test in Europe (DATE) Dresden, Germany. 2016.