Publications

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M
Milovanovic, M., Ferrer, R., Gajinov, V., Unsal, O., Cristal, A., Ayguadé, E. & Valero, M. Multithreaded software transactional memory and OpenMP. 8th MEDEA Workshop Memory Performance: Dealing With Applications, Systems And Architecture (MEDEA 2007) 81–88 (2007).at <http://capinfo.e.ac.upc.edu/PDFs/dir22/file003647.pdf>
González, I., Galluzzi, M., Cristal, A. & Valero, M. Multi-State Processor: Arquitectura sin ROB y con recuperaciones Precisas. II Congreso Español de Informática (CEDI 2007) (2007).
González, I., Galluzzi, M., Cristal, A. & Valero, M. The Multi-State Processor. 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07) 127–130 (2007).
Santana, O.J., Ramirez, A. & Valero, M. Multiple Stream Prediction. ISHPC. International Symposium on High Performance Computers (2005).
Nesbit, K.J., Moreto, M., Cazorla, F., Ramirez, A., Valero, M. & Smith, J.E. Multicore Resource Management. IEEE Micro 28, 6-16 (2008).
Moreto, M., Cazorla, F., Ramirez, A. & Valero, M. MLP-aware dynamic cache partitioning. 2008 International Conference on High Performance Embedded Architectures & Compilers (HiPEAC 2008) 337-352 (2008).
Moreto, M., Cazorla, F., Ramirez, A. & Valero, M. MLP-aware dynamic cache partitioning. International Conference on Parallel Architectures and Compilation Techniques (PACT) 418-418 (2007).
Alastruey, J.J., Monreal, T., Viñals, V. & Valero, M. Microarchitectural Support for Speculative Register Renaming. (2006).
Acosta, C., Cazorla, F., Ramirez, A. & Valero, M. MFLUSH: Handling Long-latency loads in SMT On-Chip Multiprocessors. International Conference on Parallel Processing (ICPP) 173-181 (2008).
Mir, S., Cazorla, F., Ramirez, A. & Valero, M. Metrics for the Evaluation of SMT Processors Performance. XVI Jornadas de Paralelismo (2005).
Zyulkyarov, F., Unsal, O., Cristal, A., Milovanovic, M., Ayguadé, E. & Valero, M. Memory Management for Transaction Processing Core in Heterogeneous Chip Multiprocessors. Workshop on Operating System Support for Heterogeneous Multicore Architectures (2007).
Vera, J., Cazorla, F., Pajuelo, A., Santana, O.J., Fernández, E. & Valero, M. Measuring the Performance of Multithreaded Processors. (2007).
Radojkovic, P., Cakarevic, V., Verdú, J., Pajuelo, A., Gioiosa, R., Cazorla, F., Nemirovsky, M. & Valero, M. Measuring Operating System Overhead on CMT Processors. (2008).
Cristal, A., Santana, O.J. & Valero, M. Maintaining Thousands of In-Flight Instructions. 10th International Euro-Par 2004 Conference 9–20 (2004).
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Ramírez, M.A., Cristal, A., Veidenbaum, A., Villa, L.A. & Valero, M. A Low-Power-Instruction-Queue Wakeup Mechanism. XIV Jornadas de Paralelismo 533–540 (2003).
Falcón, A., Ramirez, A. & Valero, M. A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors. 10th International Conference on High Performance Computer Architecture (HPCA-10) 244-253 (2004).
Santana, O.J., Ramirez, A., Larriba-Pey, J.L. & Valero, M. A Low-Complexity Fetch Architecture for High-Performance Superscalar Processors. ACM Transactions on Architecture and Code Optimization 1, 220-245 (2004).
Valero, M., Santana, O.J., Ramirez, A. & Larriba-Pey, J.L. A Low Complexity Fetch Architecture for High Performance Superscalar Processors. ACM Transactions on Architecture and Compiler Optimizations (TACO) 1, 220-245 (2004).
Vera, J., Cazorla, F., Pajuelo, A., Santana, O.J., Fernández, E. & Valero, M. Looking for novel ways to obtain fair measurements in multithreaded architectures. (2006).
Sánchez, F., Cabarcas, F., Ramirez, A. & Valero, M. Long DNA Sequence Comparison on Multicore Architectures. 16th international Euro-Par conference on Parallel processing (2010).at <http://dx.doi.org/10.1007/978-3-642-15291-7_24>
Moreto, M., Cazorla, F., Sakellariou, R. & Valero, M. Load Balancing Using Dynamic Cache Allocation. (2010).
Alastruey, J.J., Monreal, T., Viñals, V. & Valero, M. Limits on Early Release of Physical Registers. (2004).
Perfumo, C., Sönmez, N., Stipic, S., Unsal, O., Cristal, A., Harris, T. & Valero, M. The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment. Computing Frontiers '08 67–78 (2008).
Perfumo, C., Sönmez, N., Stipić, S., Unsal, O., Cristal, A., Harris, T. & Valero, M. The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment. 5th Conference on Computing Frontiers 67–78 (2008).at <http://capinfo.e.ac.upc.edu/PDFs/dir06/file003457.pdf>
Santana, O.J., Ramirez, A. & Valero, M. Latency Tolerant Branch Predictors. 2003 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'03) 30-39 (2003).
Falcón, A., Santana, O.J., Ramirez, A. & Valero, M. A latency conscious SMT branch predictor architecture. International Journal of High Performance Computing and Networking (IJHPCN) 2, 11-21 (2004).
Monreal, T., Viñals, V., González, J., González, A. & Valero, M. Late Allocation and Early Release of Physical Registers. (2004).
Cristal, A., Valero, M., González, A. & Llosa, J. Large Virtual ROBs by Processor Checkpointing. (2002).at <http://capinfo.e.ac.upc.edu/PDFs/dir11/file000939.pdf>
I
Luque, C., Moreto, M., Cazorla, F., Gioiosa, R. & Valero, M. ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs. (2010).
Luque, C., Moreto, M., Cazorla, F., Gioiosa, R., Buyuktosunoglu, A. & Valero, M. ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs. (2009).
Galluzzi, M., Puente, V., Santana, O.J., Acosta, C., Cristal, A., Beivide, R., Monasterio, J.A.G. & Valero, M. Introducing Kilo-instruction Multiprocessors. XV Jornadas de Paralelismo (2004).at <http://capinfo.e.ac.upc.edu/PDFs/dir19/file002977.pdf>
Gajinov, V., Milovanovic, M., Unsal, O., Cristal, A., Ayguadé, E. & Valero, M. Integrating Dataflow Abstractions into Transactional Memory. First Workshop on Systems for Future Multi-Core Architectures (SFMA'11) 1–6 (2011).
Ramírez, M.A., Cristal, A., Villa, L.A., Veidenbaum, A. & Valero, M. INSTRUCTION WAKEUP MECHANISM: Power and Timing Evaluation. CIC,s Research and Computing Science (2004).
Ramirez, A., Larriba-Pey, J.L. & Valero, M. Instruction Fetch Architectures and Code Layout Optimizations. Proceedings of the IEEE 89, 1588-1609 (2001).
Salami, E. & Valero, M. Initial Evaluation of Multimedia Extensions on VLIW Architectures. (2004).
Santana, O.J., Falcón, A., Fernández, E., Medina, P., Ramirez, A. & Valero, M. An In-Depth Evaluation of the Multi-Stage Cascaded Predictor. XII Jornadas de Paralelismo, Valencia (Spain) (2001).
Sönmez, N., Perfumo, C., Stipić, S., Cristal, A., Unsal, O. & Valero, M. Increasing the Performance of Haskell Software Transactional Memory. II Congreso Español de Informática (CEDI 2007) (2007).
Cazorla, F., Fernández, E., Ramirez, A. & Valero, M. Improving Memory Latency Aware Fetch Policies for SMT Processors. 5th International Symposium on High Performance Computing (ISHPC-V) 70-85 (2003).at <http://personals.ac.upc.edu/fcazorla/articles/fcazorla_ishpc2003.pdf>
Boneti, C., Cazorla, F. & Valero, M. Improving EDF for SMT processors. (2006).

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