Publications

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T. Hussain, Sönmez, N., Palomar, O., Unsal, O., Cristal, A., Ayguadé, E., and Valero, M., PAMS: Pattern Aware Memory System for Embedded Systems, in ReConFig - International Conference on ReConFifurable Computing and FPGAs, Cancun, Mexico, 2014.
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V. Marjanovic, Labarta, J., Ayguadé, E., and Valero, M., Overlapping Communication and Computation by Using a Hybrid MPI/SMPSs Approach. 24th International Conference on Supercomputing. Epochal Tsukuba, Tsukuba, Japan, 2010.
M. Pericàs, González, R., Cristal, A., and Valero, M., Overcoming the Memor Wall with D-KIPs, in 2005 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-2005), L'Aquila, Italy, 2005, pp. 99–102.
A. Cristal, Ortega, D., Llosa, J., and Valero, M., Out-of-Order Commit Processors, in 10th International Symposium on High Performance Computer Architecture (HPCA-10), Madrid, Spain, 2004, pp. 48–59.
A. Cristal, Martínez, J. F., Ortega, D., Llosa, J., and Valero, M., Out-of-Order Commit Processors. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2003.
F. Cazorla, Fernández, E., Ramirez, A., and Valero, M., Optimizing Long-Latency-Load-Aware Fetch Policies for SMT Processors, International Journal of High Performance Computing and Networking (IJHPCN), vol. 2, no. 2. 2004.
M. Etinski, Corbalán, J., Labarta, J., and Valero, M., Optimizing Job Performance Under a Given Power Constraint In HPC Centers. International Green Computing Conference, 2010.
A. Ramirez, Larriba-Pey, J. L., Navarro, C., Serrano, X., Torrellas, J., and Valero, M., Optimizing Instruction Fetch for Decision Support Workloads, 2nd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-2). 1999.
M. Pericàs, González, R., Cristal, A., Veidenbaum, A., and Valero, M., An Optimized Front-End Physical Register File with Banking and Writeback Filtering, in Workshop on Power-Aware Computer Systems (PACS'04), Portland, OR, United States, 2004, pp. 4–13.
A. Ramirez, Larriba-Pey, J. L., Navarro, C., Serrano, X., Torrellas, J., and Valero, M., Optimization of Instruction Fetch for Decision Support Workloads, International Conference on Parallel Processing. pp. 238-245, 1999.
A. Cristal, Martínez, J. F., Llosa, J., and Valero, M., Optimal Use of Registers in Aggressive Superscalar Processors, in XIV Jornadas de Paralelismo, Leganés, Spain, 2003, pp. 553–558.
P. Radojkovic, Cakarevic, V., Moreto, M., Verdu, J., Pajuelo, A., Cazorla, F., Nemirovsky, M., and Valero, M., Optimal Task Assignment in Multithreaded Processors: A Statistical Approach, Architectural Support for Programming Languages and Operating Systems (ASPLOS). ACM, 2012.
P. Radojkovic, Cakarevic, V., Moretó, M., Verdú, J., Pajuelo, A., Cazorla, F. J., Nemirovsky, M., and Valero, M., Optimal Task Assignment in Multithreaded Processors: A Statistical Approach, 17th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-2012). London, United Kingdom, 2012.
M. Moreto, Cazorla, F., Ramirez, A., and Valero, M., Online Prediction of Throughput for Different Cache Sizes, XVIII Jornadas de Paralelismo. Zaragoza, Spain, 2007.
M. Moreto, Cazorla, F., Ramirez, A., and Valero, M., Online Prediction of Applications Cache Utility, International Symposium on Systems, Architectures, MOdeling and Simulation (SAMOS). IEEE Computer Society Press, pp. 169-177, 2007.
N. Markovic, Nemirovsky, D., González, R., Ünsal, O. S., Valero, M., and Cristal, A., Object Orienteed Execution Model (OOM), 2nd Workshop on New Directions in Computer Architecture (NDCA-2) Held in Conjunction with the 38th International Symposium on Computer Architecture (ISCA-38). San Jose, California, Sunday June 5th, 2011.
N. Markovic, Nemirovsky, D., González, R., Unsal, O., Valero, M., and Cristal, A., Object Oriented execution Model (OOM), New Directions in Computer Architecture (NDCA-2). San Jose, California, United States, 2011.
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J. Vera, Cazorla, F., Pajuelo, A., Santana, O. J., Fernández, E., and Valero, M., A Novel Evaluation Methodology to Obtain Fair Measurements in Multithreaded Architectures. In Workshop on Modeling, Benchmarking and Simulation (MoBS)2006. Held in conjunction with ISCA, Boston, USA, 2006.
M. A. Ramírez, Cristal, A., Valero, M., Veidenbaum, A., and Villa, L. A., A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation, in IEEE International Conference on Computer Design (ICCD-2005), San José, CA, United States, 2005, pp. 647–653.
M. Milovanovic, Ferrer, R., Gajinov, V., Unsal, O., Cristal, A., Ayguadé, E., and Valero, M., Nebelung: Execution Environment for Transactional OpenMP, International Journal of Parallel Programming, vol. 36, pp. 326–346, 2008.
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M. Milovanovic, Ferrer, R., Gajinov, V., Unsal, O., Cristal, A., Ayguadé, E., and Valero, M., Multithreaded software transactional memory and OpenMP, in 8th MEDEA Workshop Memory Performance: Dealing With Applications, Systems And Architecture (MEDEA 2007), Brasov, Romania, 2007, pp. 81–88.
I. González, Galluzzi, M., Cristal, A., and Valero, M., Multi-State Processor: Arquitectura sin ROB y con recuperaciones Precisas, in II Congreso Español de Informática (CEDI 2007), Zaragoza, Spain, 2007.
I. González, Galluzzi, M., Cristal, A., and Valero, M., The Multi-State Processor, in 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07), L'Aquila, Italy, 2007, pp. 127–130.
O. J. Santana, Ramirez, A., and Valero, M., Multiple Stream Prediction, ISHPC. International Symposium on High Performance Computers. Springer-Verlag, 2005.
K. J. Nesbit, Moreto, M., Cazorla, F., Ramirez, A., Valero, M., and Smith, J. E., Multicore Resource Management, IEEE Micro, vol. 28, no. 3. pp. 6-16, 2008.
M. Moreto, Cazorla, F., Ramirez, A., and Valero, M., MLP-aware dynamic cache partitioning, International Conference on Parallel Architectures and Compilation Techniques (PACT). Brasov, Romania, pp. 418-418, 2007.
M. Moreto, Cazorla, F., Ramirez, A., and Valero, M., MLP-aware dynamic cache partitioning, 2008 International Conference on High Performance Embedded Architectures & Compilers (HiPEAC 2008). Goteborg, Sweden, pp. 337-352, 2008.
J. J. Alastruey, Monreal, T., Viñals, V., and Valero, M., Microarchitectural Support for Speculative Register Renaming. IPDPS07. IEEE International Parallel and Distributed Processing Sympsium. Long Beach, USA, 2006.
C. Acosta, Cazorla, F., Ramirez, A., and Valero, M., MFLUSH: Handling Long-latency loads in SMT On-Chip Multiprocessors., International Conference on Parallel Processing (ICPP). pp. 173-181, 2008.
S. Mir, Cazorla, F., Ramirez, A., and Valero, M., Metrics for the Evaluation of SMT Processors Performance, XVI Jornadas de Paralelismo. 2005.
F. Zyulkyarov, Unsal, O., Cristal, A., Milovanovic, M., Ayguadé, E., and Valero, M., Memory Management for Transaction Processing Core in Heterogeneous Chip Multiprocessors, in Workshop on Operating System Support for Heterogeneous Multicore Architectures, Brasov, Romania, 2007.
J. Vera, Cazorla, F., Pajuelo, A., Santana, O. J., Fernández, E., and Valero, M., Measuring the Performance of Multithreaded Processors. In SPEC Benchmark Workshop (in conjunction with the Annual Meeting of the Standard Performance Evaluation Corporation (SPEC)), Austin, USA, 2007.
P. Radojkovic, Cakarevic, V., Verdú, J., Pajuelo, A., Gioiosa, R., Cazorla, F., Nemirovsky, M., and Valero, M., Measuring Operating System Overhead on CMT Processors. In 20th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). Campo Grande, Brazil, 2008.
T. Hussain, Palomar, O., Unsal, O., Cristal, A., Ayguadé, E., and Valero, M., MAPC. Memory Access Pattern based Controller, in 24th International Conference on Field Programmable Logic and Applications (FPL), 2014, Munich, Germany, 2014, pp. 1–4.
A. Cristal, Santana, O. J., and Valero, M., Maintaining Thousands of In-Flight Instructions, in 10th International Euro-Par 2004 Conference, Pisa, Italy, 2004, pp. 9–20.
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M. A. Ramírez, Cristal, A., Veidenbaum, A., Villa, L. A., and Valero, M., A Low-Power-Instruction-Queue Wakeup Mechanism, in XIV Jornadas de Paralelismo, Leganés, Spain, 2003, pp. 533–540.
A. Falcón, Ramirez, A., and Valero, M., A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors, 10th International Conference on High Performance Computer Architecture (HPCA-10). Madrid (Spain), pp. 244-253, 2004.
O. J. Santana, Ramirez, A., Larriba-Pey, J. L., and Valero, M., A Low-Complexity Fetch Architecture for High-Performance Superscalar Processors, ACM Transactions on Architecture and Code Optimization, vol. 1, no. 2. pp. 220-245, 2004.
M. Valero, Santana, O. J., Ramirez, A., and Larriba-Pey, J. L., A Low Complexity Fetch Architecture for High Performance Superscalar Processors, ACM Transactions on Architecture and Compiler Optimizations (TACO), vol. 1, no. 2. pp. 220-245, 2004.
J. Vera, Cazorla, F., Pajuelo, A., Santana, O. J., Fernández, E., and Valero, M., Looking for novel ways to obtain fair measurements in multithreaded architectures. XVII Jornadas de Paralelismo, 2006.
F. Sánchez, Cabarcas, F., Ramirez, A., and Valero, M., Long DNA Sequence Comparison on Multicore Architectures, 16th international Euro-Par conference on Parallel processing. 2010.
M. Moreto, Cazorla, F., Sakellariou, R., and Valero, M., Load Balancing Using Dynamic Cache Allocation. ACM International Conference on Computing Frontiers (CF), 2010.
J. J. Alastruey, Monreal, T., Viñals, V., and Valero, M., Limits on Early Release of Physical Registers. XV Jornadas de Paralelismo, 2004.
C. Perfumo, Sönmez, N., Stipić, S., Unsal, O., Cristal, A., Harris, T., and Valero, M., The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment, in 5th Conference on Computing Frontiers, Ischia, Italy, 2008, pp. 67–78.
C. Perfumo, Sönmez, N., Stipic, S., Unsal, O., Cristal, A., Harris, T., and Valero, M., The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment, Computing Frontiers '08. pp. 67–78, 2008.
O. J. Santana, Ramirez, A., and Valero, M., Latency Tolerant Branch Predictors, 2003 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'03). Kauai, Hawaii (United States), pp. 30-39, 2003.
A. Falcón, Santana, O. J., Ramirez, A., and Valero, M., A latency conscious SMT branch predictor architecture, International Journal of High Performance Computing and Networking (IJHPCN), vol. 2, no. 1. pp. 11-21, 2004.
T. Monreal, Viñals, V., González, J., González, A., and Valero, M., Late Allocation and Early Release of Physical Registers. IEEE Transactions on Computers, 2004.
A. Cristal, Valero, M., González, A., and Llosa, J., Large Virtual ROBs by Processor Checkpointing. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2002.

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