Publications

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2003
A. Cristal, Martínez, J. F., Llosa, J., and Valero, M., Ephemeral Registers with Multicheckpointing. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2003.
F. Cazorla, Fernández, E., Ramirez, A., and Valero, M., Improving Memory Latency Aware Fetch Policies for SMT Processors, 5th International Symposium on High Performance Computing (ISHPC-V). Springer-Verlag, Tokyo, Japan, pp. 70-85, 2003.
A. Cristal, Ortega, D., Llosa, J., and Valero, M., Kilo-instruction Processors, in 5th International Symposium on High Performance Computing (ISHPC-V), Tokio, Japan, 2003, pp. 10–25.
O. J. Santana, Ramirez, A., and Valero, M., Latency Tolerant Branch Predictors, 2003 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'03). Kauai, Hawaii (United States), pp. 30-39, 2003.
M. A. Ramírez, Cristal, A., Veidenbaum, A., Villa, L. A., and Valero, M., A Low-Power-Instruction-Queue Wakeup Mechanism, in XIV Jornadas de Paralelismo, Leganés, Spain, 2003, pp. 533–540.
A. Cristal, Martínez, J. F., Llosa, J., and Valero, M., Optimal Use of Registers in Aggressive Superscalar Processors, in XIV Jornadas de Paralelismo, Leganés, Spain, 2003, pp. 553–558.
A. Cristal, Martínez, J. F., Ortega, D., Llosa, J., and Valero, M., Out-of-Order Commit Processors. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2003.
M. A. Ramírez, Cristal, A., Veidenbaum, A., Villa, L. A., and Valero, M., A Simple Low-Energy Instruction Wakeup Mechanism, in 5th International Symposium on High Performance Computing (ISHPC-V), Tokio, Japan, 2003, pp. 99–112.
A. Falcón, Santana, O. J., Ramirez, A., and Valero, M., Tolerating branch predictor latency on SMT, 5th International Symposium on High Performance Computing (ISHPC-V). Tokio (Japan), pp. 86-98, 2003.
2002
A. García, Fernández, E., Medina, P., Ramirez, A., and Valero, M., Analisis y caracterización de los bucles, XIII Jornadas de Paralelismo. Lleida (Spain), 2002.
P. Knijnenburg, Ramirez, A., Larriba-Pey, J. L., and Valero, M., Branch classification for SMT fetch gating, 6th Workshop on Multithreaded Execution, Architecture and Compilation (MTEAC6). Istambul (Turkey), 2002.
P. Knijnenburg, Ramirez, A., Latorre, F., Larriba-Pey, J. L., and Valero, M., Branch Classification to Control Instruction Fetch in Simultaneous Multithreaded Architectures, International Workshop on Innovative Architecture (IWIA 2002). Kohala Coast, Hawaii (United States), pp. 67-76, 2002.
H. Vandierendonck, Ramirez, A., Bosschere, K. D., and Valero, M., A comparative study of redundancy in trace caches, Intl. Euro-Par Conference. Paderborn (Germany), pp. 512-516, 2002.
O. J. Santana, Falcón, A., Fernández, E., Medina, P., Ramirez, A., and Valero, M., A Comprehensive Analysis of Indirect Branch Prediction, 4th International Symposium on High Performance Computing (ISHPC-4). Springer-Verlag, Kansai Science City (Japan), pp. 133-141, 2002.
F. Cazorla, Medina, P., Fernández, E., Ramirez, A., and Valero, M., Estudio y evaluación de mecanismos de control de la Especulación, In XIII Jornadas de Paralelismo, Lleida (Spain). 2002.
A. Ramirez, Santana, O. J., Larriba-Pey, J. L., and Valero, M., Fetching Instruction Streams, 35th Annual International Symposium on Microarchitecture (MICRO-35). Istambul (Turkey), pp. 371-382, 2002.
A. Cristal, Valero, M., González, A., and Llosa, J., Large Virtual ROBs by Processor Checkpointing. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2002.
A. Cristal and Valero, M., ROBs Virtuales utilizando checkpoints, in XIII Jornadas de Paralelismo, Lleida, Spain, 2002.
A. Ramirez, Larriba-Pey, J. L., Navarro, C., Valero, M., and Torrellas, J., Software Trace Cache for Commercial Applications, International Journal of Parallel Programming, vol. 30, no. 5. pp. 373-395, 2002.
A. Falcón, Santana, O. J., Medina, P., Fernández, E., Ramirez, A., and Valero, M., Studying New Ways for Improving Adaptive History Length Branch Predictors, 4th International Symposium on High Performance Computing (ISHPC-4). Kansai Science City (Japan), pp. 271-279, 2002.
2000
A. Ramirez, Larriba-Pey, J. L., and Valero, M., The Effect of Code Reordering on Branch Prediction, International Conference on Parallel Architectures and Compilation Techniques (PACT 2000). pp. 189-198, 2000.
C. Navarro, Ramirez, A., Larriba-Pey, J. L., and Valero, M., Fetch Engines and Databases, 3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3). 2000.
C. Navarro, Ramirez, A., Larriba-Pey, J. L., and Valero, M., On the Performance of Fetch Engines Running DSS Workloads, 6th International Euro-Par Conference (EuroPar'2000). Springer-Verlag, pp. 591-595, 2000.
A. Ramirez, Larriba-Pey, J. L., and Valero, M., Semi-static Branch Prediction for Optimized Code Layouts, 3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3). 2000.
A. Ramirez, Larriba-Pey, J. L., and Valero, M., A Stream Processor Front-end, IEEE Technical Committee on Computer Architecture Newsletter. pp. 10-13, 2000.
A. Ramirez, Larriba-Pey, J. L., and Valero, M., Trace Cache Redundancy: Red & Blue Traces, Sixth International Symposium on High-Performance Computer Architecture (HPCA'2000). pp. 325-333, 2000.

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