Publications

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2002
A. Cristal, Valero, M., González, A., and Llosa, J., Large Virtual ROBs by Processor Checkpointing. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2002.
A. Cristal and Valero, M., ROBs Virtuales utilizando checkpoints, in XIII Jornadas de Paralelismo, Lleida, Spain, 2002.
A. Ramirez, Larriba-Pey, J. L., Navarro, C., Valero, M., and Torrellas, J., Software Trace Cache for Commercial Applications, International Journal of Parallel Programming, vol. 30, no. 5. pp. 373-395, 2002.
A. Falcón, Santana, O. J., Medina, P., Fernández, E., Ramirez, A., and Valero, M., Studying New Ways for Improving Adaptive History Length Branch Predictors, 4th International Symposium on High Performance Computing (ISHPC-4). Kansai Science City (Japan), pp. 271-279, 2002.
2000
A. Ramirez, Larriba-Pey, J. L., and Valero, M., The Effect of Code Reordering on Branch Prediction, International Conference on Parallel Architectures and Compilation Techniques (PACT 2000). pp. 189-198, 2000.
C. Navarro, Ramirez, A., Larriba-Pey, J. L., and Valero, M., Fetch Engines and Databases, 3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3). 2000.
C. Navarro, Ramirez, A., Larriba-Pey, J. L., and Valero, M., On the Performance of Fetch Engines Running DSS Workloads, 6th International Euro-Par Conference (EuroPar'2000). Springer-Verlag, pp. 591-595, 2000.
A. Ramirez, Larriba-Pey, J. L., and Valero, M., Semi-static Branch Prediction for Optimized Code Layouts, 3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3). 2000.
A. Ramirez, Larriba-Pey, J. L., and Valero, M., A Stream Processor Front-end, IEEE Technical Committee on Computer Architecture Newsletter. pp. 10-13, 2000.
A. Ramirez, Larriba-Pey, J. L., and Valero, M., Trace Cache Redundancy: Red & Blue Traces, Sixth International Symposium on High-Performance Computer Architecture (HPCA'2000). pp. 325-333, 2000.

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