Publications

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2005
M. Pericàs, Cristal, A., González, R., Jiménez, D. A., and Valero, M., Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor, in 6th International Symposium on High Performance Computing (ISHPC-VI 2005), Nara, Japan, 2005, pp. 56–67.
E. Vallejo, Galluzzi, M., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J. E., and Valero, M., Implementing Kilo-Instruction Multiprocessors, in International Conference on Pervasive Services (ICPS 2005), Santorini, Greece, 2005, pp. 325–336.
A. Cristal, Santana, O. J., Cazorla, F., Galluzzi, M., Ramírez, T., Pericàs, M., and Valero, M., Kilo-instruction Processors: Overcoming the Memory Wall, IEEE Micro, vol. 25. pp. 48–57, 2005.
E. Vallejo, Galluzzi, M., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J. E., and Valero, M., KIMP: Multicheckpointing Multiprocessors, in XVI Jornadas de Paralelismo, Granada, Spain, 2005.
M. A. Ramírez, Cristal, A., Valero, M., Veidenbaum, A., and Villa, L. A., A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation, in IEEE International Conference on Computer Design (ICCD-2005), San José, CA, United States, 2005, pp. 647–653.
M. Pericàs, González, R., Cristal, A., and Valero, M., Overcoming the Memor Wall with D-KIPs, in 2005 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-2005), L'Aquila, Italy, 2005, pp. 99–102.
A. García, Medina, P., Fernández, E., Santana, O. J., Cristal, A., and Valero, M., Towards the Loop Processor Architecture, in XVI Jornadas de Paralelismo, Granada, Spain, 2005.
2004
M. Pericàs, González, R., Cristal, A., Veidenbaum, A., and Valero, M., Banked Front-End Register File. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2004.
A. Cristal, Martínez, J. F., Llosa, J., and Valero, M., A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors, ACM SIGARCH Computer Architecture News, vol. 32, pp. 3–10, 2004.
R. González, Cristal, A., Veidenbaum, A., Pericàs, M., and Valero, M., A clustered Processor based on Content-Aware Register File. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2004.
A. Cristal, Santana, O. J., and Valero, M., A Comprehensive Description of Kilo-Instruction Processors, in 5o Congreso Nacional de Computación, Mexico City, Mexico, 2004, pp. 144–154.
R. González, Cristal, A., Ortega, D., Veidenbaum, A., and Valero, M., A Content Aware Integer Register File Organization, in International Symposium on Computer Architecture (ISCA 2004), München, Germany, 2004, pp. 314–324.
M. A. Ramírez, Cristal, A., Villa, L. A., Veidenbaum, A., and Valero, M., Direct Instruction Wakeup for OOO processors, in Innovative Architecture for Future Generation High-Performance Processors and System, Maui, Hawaii, United States, 2004.
M. Galluzzi, Puente, V., Cristal, A., Beivide, R., Monasterio, J. A. G., and Valero, M., Evaluating Kilo-instruction Multiprocessors, in 3rd Workshop on Memory Performance Issues (WMPI-2004), München, Germany, 2004, pp. 72–79.
M. Galluzzi, Puente, V., Cristal, A., Beivide, R., Monasterio, J. A. G., and Valero, M., A first glance at Kilo-instruction based multiprocessors, in International Conference on Computing Frontiers 2004 (CF'04), Ischia, Italy, 2004, pp. 212–221.
A. Cristal, Llosa, J., Valero, M., and Ortega, D., Future ILP processors, International Journal of High Performance Computing and Networking, vol. 2, pp. 1–10, 2004.
M. A. Ramírez, Cristal, A., Villa, L. A., Veidenbaum, A., and Valero, M., INSTRUCTION WAKEUP MECHANISM: Power and Timing Evaluation, in CIC,s Research and Computing Science, 2004.
M. Galluzzi, Puente, V., Santana, O. J., Acosta, C., Cristal, A., Beivide, R., Monasterio, J. A. G., and Valero, M., Introducing Kilo-instruction Multiprocessors, in XV Jornadas de Paralelismo, Almería, Spain, 2004.
A. Cristal, Santana, O. J., and Valero, M., Maintaining Thousands of In-Flight Instructions, in 10th International Euro-Par 2004 Conference, Pisa, Italy, 2004, pp. 9–20.
M. Pericàs, González, R., Cristal, A., Veidenbaum, A., and Valero, M., An Optimized Front-End Physical Register File with Banking and Writeback Filtering, in Workshop on Power-Aware Computer Systems (PACS'04), Portland, OR, United States, 2004, pp. 4–13.
A. Cristal, Ortega, D., Llosa, J., and Valero, M., Out-of-Order Commit Processors, in 10th International Symposium on High Performance Computer Architecture (HPCA-10), Madrid, Spain, 2004, pp. 48–59.
M. A. Ramírez, Cristal, A., Valero, M., Veidenbaum, A., and Villa, L. A., A partitioned instruction queue to reduce instruction wakeup energy, International Journal of High Performance Computing and Networking, vol. 1, pp. 153–161, 2004.
R. González, Cristal, A., Pericàs, M., Veidenbaum, A., and Valero, M., Scalable Distributed Register File, in 5th Workshop on Complexity-Effective Design, München, Germany, 2004, pp. 5–14.
A. Cristal, Santana, O. J., Valero, M., and Martínez, J. F., Toward Kilo-instruction Processors, ACM Transactions on Architecture and Code Optimization, vol. 1, pp. 368–396, 2004.
2003
R. González, Cristal, A., Ortega, D., and Valero, M., Arquitecturas Basadas en el Contenido, in XIV Jornadas de Paralelismo, Leganés, Spain, 2003, pp. 541–546.
A. Cristal, Martínez, J. F., Llosa, J., and Valero, M., A Case for Resource Conscious Out-of-Order Processor, in MEDEA Workshop MEmory performance: DEaling with Applications , systems and architecture (MEDEA 2003), New Orleans, LA, United States, 2003.
A. Cristal, Martínez, J. F., Llosa, J., and Valero, M., A Case for Resource-conscious Out-of-order Processors, Computer Architecture Letters, vol. 2, 2003.
A. Cristal, Martínez, J. F., Llosa, J., and Valero, M., A Case for Resource-conscious Out-of-order Processors. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2003.
R. González, Cristal, A., Ortega, D., and Valero, M., Content Aware Register File Organisation. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2003.
A. Cristal, Martínez, J. F., Llosa, J., and Valero, M., Ephemeral Registers with Multicheckpointing. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2003.
A. Cristal, Ortega, D., Llosa, J., and Valero, M., Kilo-instruction Processors, in 5th International Symposium on High Performance Computing (ISHPC-V), Tokio, Japan, 2003, pp. 10–25.
M. A. Ramírez, Cristal, A., Veidenbaum, A., Villa, L. A., and Valero, M., A Low-Power-Instruction-Queue Wakeup Mechanism, in XIV Jornadas de Paralelismo, Leganés, Spain, 2003, pp. 533–540.
A. Cristal, Martínez, J. F., Llosa, J., and Valero, M., Optimal Use of Registers in Aggressive Superscalar Processors, in XIV Jornadas de Paralelismo, Leganés, Spain, 2003, pp. 553–558.
A. Cristal, Martínez, J. F., Ortega, D., Llosa, J., and Valero, M., Out-of-Order Commit Processors. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2003.
M. A. Ramírez, Cristal, A., Veidenbaum, A., Villa, L. A., and Valero, M., A Simple Low-Energy Instruction Wakeup Mechanism, in 5th International Symposium on High Performance Computing (ISHPC-V), Tokio, Japan, 2003, pp. 99–112.
2002
A. Cristal, Valero, M., González, A., and Llosa, J., Large Virtual ROBs by Processor Checkpointing. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2002.
A. Cristal and Valero, M., ROBs Virtuales utilizando checkpoints, in XIII Jornadas de Paralelismo, Lleida, Spain, 2002.
1997
A. Cristal, Un simulador de un procesador similar al MIPS R10000. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 1997.
1996
A. Cristal, Síntesis de Redes de Petri. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 1996.

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