Publications

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2015
D. Prat, Ortega, C., Casas, M., Moreto, M., and Valero, M., Adaptive and application dependent runtime guided hardware prefetcher reconfiguration on the IBM POWER7, 6th International Workshop on Adaptive Self-tuning Computing Systems. arXiv.org, Amsterdam, Netherlands, pp. 1–6, 2015.
2014
Q. Liu, Moreto, M., Abella, J., Cazorla, F. J., and Valero, M., DReAM: Per-Task DRAM Energy Metering in Multicore Systems, 20th International EUROPAR Conference. European Conference on Parallel and Distributed Computing. Springer, Porto, Portugal, pp. 111–123, 2014.
T. Grass, Rico, A., Casas, M., Moreto, M., and Ramirez, A., Evaluating Execution Time Predictability of Task-Based Programs, 7th International Workshop on Multi-/Many-Core Computing Systems. Springer International Publishing, Porto, Portugal, pp. 218–229, 2014.
D. Roca, Nemirovsky, M., Moreto, M., and Casas, M., High level queuing architecture model for high-end processors. 2014.
M. Valero, Moreto, M., Casas, M., Ayguadé, E., and Labarta, J., Runtime-Aware Architectures: A First Approach, International Journal on Supercomputing Frontiers and Innovations, vol. 1. pp. 29-44, 2014.
T. Grass, Rico, A., Casas, M., Moreto, M., and Ramirez, A., Task Sampling: Computer Architecture Simulation in the Many-Core Era, Advanced Computer Architecture and Compilation for for High-Performance and Embedded Systems. Academic Press Ghent (Belgium), Fiuggi, Italy, pp. 165–168, 2014.
2013
C. Luque, Moreto, M., Cazorla, F. J., and Valero, M., Fair CPU Time Accounting in CMP+SMT Processors, ACM Trans. Archit. Code Optim., vol. 9. ACM, New York, NY, USA, pp. 50:1–50:25, 2013.
H. Cook, Moreto, M., Bird, S., Dao, K., Patterson, D. A., and Asanovic, K., A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness, Proceedings of the 40th Annual International Symposium on Computer Architecture. ACM, New York, NY, USA, pp. 308–319, 2013.
Q. Liu, Moreto, M., Jiménez, V., Abella, J., Cazorla, F. J., and Valero, M., Hardware Support for Accurate Per-task Energy Metering in Multicore Systems, ACM Trans. Archit. Code Optim., vol. 10. ACM, New York, NY, USA, pp. 34:1–34:27, 2013.
Q. Liu, Jimenez, V., Moreto, M., Abella, J., Francisco,, and Cazorla, F. J., Per-task Energy Accounting in Computing Systems, In IEEE Computer Architecture Letters (CAL), vol. 13. pp. 1-6, 2013.
C. Camarero, Vallejo, E., Martinez, C., Moreto, M., and Beivide, R., Task Mapping in Rectangular Twisted Tori, Proceedings of the High Performance Computing Symposium. Society for Computer Simulation International, San Diego, CA, USA, pp. 15:1–15:11, 2013.
2009
C. Luque, Moreto, M., Cazorla, F., Gioiosa, R., Buyuktosunoglu, A., and Valero, M., CPU accounting in CMP Processors. In IEEE Computer Architecture Letters. Volume 9, 2009.
M. Moreto, Cazorla, F., Ramirez, A., Sakellariou, R., and Valero, M., FlexDCP: a QoS framework for CMP architectures, ACM SIGOPS Operating System Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors, vol. 43, no. 2. pp. 0163-5980, 2009.
C. Luque, Moreto, M., Cazorla, F., Gioiosa, R., Buyuktosunoglu, A., and Valero, M., ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs. In International Symposium on Parallel Architectures and Compilation Techniques, North Carolina, USA, 2009.
K. Kedzierski, Moreto, M., Cazorla, F., and Valero, M., pseudo-LRU based Cache Partitioning Algorithms. In International Symposium on Parallel Architectures and Compilation Techniques, North Carolina, USA, 2009.
2008
P. A. Castillo, Mora, A. M., Merelo, J. J., Laredo, J. L., Moreto, M., Cazorla, F., Valero, M., and McKee, S. A., Architecture performance prediction using evolutionary artificial neural networks. In European Workshop on Hardware Optimization Techniques (EVOHot). Napoli, Italy, 2008.
M. Moreto, Cazorla, F., Ramirez, A., and Valero, M., Dynamic Cache Partitioning Based on the MLP on Cache Misses., Transactions on HiPEAC, vol. 3, no. 1. pp. 1-21, 2008.
P. A. Castillo, Merelo, J. J., Moreto, M., Cazorla, F., Valero, M., Mora, A. M., Laredo, J. L., and McKee, S. A., Evolutionary system for prediction and optimization of hardware architecture performance. In IEEE Congress on Evolutionary Computation (CEC). Hong Kong, 2008.
M. Moreto, Cazorla, F., Ramirez, A., and Valero, M., MLP-aware dynamic cache partitioning, 2008 International Conference on High Performance Embedded Architectures & Compilers (HiPEAC 2008). Goteborg, Sweden, pp. 337-352, 2008.
K. J. Nesbit, Moreto, M., Cazorla, F., Ramirez, A., Valero, M., and Smith, J. E., Multicore Resource Management, IEEE Micro, vol. 28, no. 3. pp. 6-16, 2008.
K. J. Nesbit, Moreto, M., Cazorla, F., Ramirez, A., Valero, M., and Smith, J. E., Virtual Private Machines: Hardware/Software Interactions in the Multicore Era. IEEE Micro, special issue on Interaction of Computer Architecture and Operating System in the Manycore Era, vol. 38, no. 3, 2008.
2007
M. Moreto, Cazorla, F., Ramirez, A., and Valero, M., Explaining Dynamic Cache Partitioning Speed Ups, IEEE Computer Architecture Letters, vol. 6, no. 1. pp. 1-12, 2007.
M. Moreto, Cazorla, F., Ramirez, A., and Valero, M., MLP-aware dynamic cache partitioning, International Conference on Parallel Architectures and Compilation Techniques (PACT). Brasov, Romania, pp. 418-418, 2007.
M. Moreto, Cazorla, F., Ramirez, A., and Valero, M., Online Prediction of Applications Cache Utility, International Symposium on Systems, Architectures, MOdeling and Simulation (SAMOS). IEEE Computer Society Press, pp. 169-177, 2007.
M. Moreto, Cazorla, F., Ramirez, A., and Valero, M., Online Prediction of Throughput for Different Cache Sizes, XVIII Jornadas de Paralelismo. Zaragoza, Spain, 2007.
2006
M. Moreto, Ramirez, A., and Valero, M., Reducing Simulation Time, 2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06). 2006.