Publications
Export 31 results:
Sort by: Author Title Type [ Year
] Filters: Author is Enrique Fernández [Clear All Filters]
FAME: FAirly MEasuring Multithreaded Architectures. (2007).at <http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4336221>
On the Problem of Minimizing Workload Execution Time in SMT Processors. International Conference on Embedded Computer Systems: Architectures, Modelling, and Simulation (SAMOS VII) 66-73 (2007).at <http://dx.doi.org/10.1109/ICSAMOS.2007.4285735>
Reducing the Activity of Instruction Renaming in Loop Structures. II Congreso Español de Informática (CEDI 2007) (2007).
Predictable Performance in SMT processors: Synergy Between the OS and SMTs. IEEE Transactions on Computers 55, 785-799 (2006).
Architectural Support for Real-Time Task Scheduling in SMT Processors. International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES-2005) (2005).
Dynamically Controlled Resource Allocation in SMT. XVI Jornadas de Paralelismo. Granada (2005).
Quality of service for Simultaneous Multithreading Processors. ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems 67-70 (2005).
Towards the Loop Processor Architecture. XVI Jornadas de Paralelismo (2005).
Approaching a Smart Sharing of Resources in SMT Processors. Workshop on Complexity-Effective Design (WCED) (2004).
DCache Warn: An I-Fetch Policy To Increase SMT Efficiency. 18th International Parallel and Distributed Processing Symposium (IPDPS-2004) (2004).
Dynamically Controlled Resource Allocation in SMT Processors. 37th Annual International Symposium on Microarchitecture (MICRO-37) 171-182 (2004).
Implicit vs. Explicit Resource Allocation in SMT Processors. 2004 Euromicro Symposium on Digital Systems Design (DSD 2004) 44-51 (2004).
Optimizing Long-Latency-Load-Aware Fetch Policies for SMT Processors. International Journal of High Performance Computing and Networking (IJHPCN) 2, (2004).
Predictable Performance in SMT Processors. Computing Frontiers (CF'04) (2004).
Throughput versus Quality of Service in SMT processors. Euromicro-DSD (Digital System Design) (2004).
Improving Memory Latency Aware Fetch Policies for SMT Processors. 5th International Symposium on High Performance Computing (ISHPC-V) 70-85 (2003).at <http://personals.ac.upc.edu/fcazorla/articles/fcazorla_ishpc2003.pdf>
Analisis y caracterización de los bucles. XIII Jornadas de Paralelismo (2002).
A Comprehensive Analysis of Indirect Branch Prediction. 4th International Symposium on High Performance Computing (ISHPC-4) 133-141 (2002).
Estudio y evaluación de mecanismos de control de la Especulación. In XIII Jornadas de Paralelismo, Lleida (Spain) (2002).
Studying New Ways for Improving Adaptive History Length Branch Predictors. 4th International Symposium on High Performance Computing (ISHPC-4) 271-279 (2002).
An Analysis of Dynamic History Length Fitting. XII Jornadas de Paralelismo, Valencia (Spain) (2001).
An In-Depth Evaluation of the Multi-Stage Cascaded Predictor. XII Jornadas de Paralelismo, Valencia (Spain) (2001).


