Publications

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Author Title Type [ Year(Asc)]
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2004
Cazorla, F., Fernández, E., Ramirez, A. & Valero, M. Approaching a Smart Sharing of Resources in SMT Processors. Workshop on Complexity-Effective Design (WCED) (2004).
Cazorla, F., Fernández, E., Ramirez, A. & Valero, M. DCache Warn: An I-Fetch Policy To Increase SMT Efficiency. 18th International Parallel and Distributed Processing Symposium (IPDPS-2004) (2004).
Cazorla, F., Ramirez, A., Valero, M. & Fernández, E. Dynamically Controlled Resource Allocation in SMT Processors. 37th Annual International Symposium on Microarchitecture (MICRO-37) 171-182 (2004).
Cazorla, F. et al. Implicit vs. Explicit Resource Allocation in SMT Processors. 2004 Euromicro Symposium on Digital Systems Design (DSD 2004) 44-51 (2004).
Cazorla, F., Fernández, E., Ramirez, A. & Valero, M. Optimizing Long-Latency-Load-Aware Fetch Policies for SMT Processors. International Journal of High Performance Computing and Networking (IJHPCN) 2, (2004).
Cazorla, F. et al. Predictable Performance in SMT Processors. Computing Frontiers (CF'04) (2004).
Cazorla, F. et al. QoS for High-Performance SMT Processors in Embedded Systems. IEEE Micro 24, 24-31 (2004).
Fernández, E. et al. Throughput versus Quality of Service in SMT processors. Euromicro-DSD (Digital System Design) (2004).
2001
Falcón, A. et al. An Analysis of Dynamic History Length Fitting. XII Jornadas de Paralelismo, Valencia (Spain) (2001).
Santana, O. J. et al. An In-Depth Evaluation of the Multi-Stage Cascaded Predictor. XII Jornadas de Paralelismo, Valencia (Spain) (2001).