Publications

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2008
I. González, Galluzzi, M., Veidenbaum, A., Ramírez, M. A., Cristal, A., and Valero, M., A distributed processor state management architecture for large-window processors, in 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41), Lake Como, Italy, 2008, pp. 11–22.
I. González, Galluzzi, M., Veidenbaum, A., Ramirez, A., Cristal, A., and Valero, M., A distributed processor state management architecture for large-window processors, in 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41), Lake Como, Italy, 2008, pp. 11–22.
E. Vallejo, Harris, T., Cristal, A., Unsal, O., and Valero, M., Hybrid Transactional Memory to accelerate safe lock-based transactions, in 3rd ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2008), Salt Lake City, UT, United States, 2008.
C. Perfumo, Sönmez, N., Stipic, S., Unsal, O., Cristal, A., Harris, T., and Valero, M., The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment, Computing Frontiers '08. pp. 67–78, 2008.
C. Perfumo, Sönmez, N., Stipić, S., Unsal, O., Cristal, A., Harris, T., and Valero, M., The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment, in 5th Conference on Computing Frontiers, Ischia, Italy, 2008, pp. 67–78.
M. Milovanovic, Ferrer, R., Gajinov, V., Unsal, O., Cristal, A., Ayguadé, E., and Valero, M., Nebelung: Execution Environment for Transactional OpenMP, International Journal of Parallel Programming, vol. 36, pp. 326–346, 2008.
E. Vallejo, Sanyal, S., Harris, T., Vallejo, F., Beivide, R., Unsal, O., Cristal, A., and Valero, M., Towards Fair Scalable Locking, in Workshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods (EPHAM 2008), Boston, MA, United States, 2008.
G. Kestor, Unsal, O., Cristal, A., and Valero, M., Transactional Look-based Parallel Program, in Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008, L'Aquila, Italy, 2008, pp. 71–75.
M. Pericas, González, R., Cazorla, F., Cristal, A., Veidenbaum, A., Jiménez, D. A., and Valero, M., A two-level Load/Store Queue based on Execution Locality. In International Symposium on Computer Architecture. Beijing, China, 2008.
M. Pericàs, Cristal, A., Cazorla, F., González, R., Veidenbaum, A., Jiménez, D. A., and Valero, M., A Two-Level Load/Store Queue Based on Execution Locality, in The 35th International Symposium on Computer Architecture (ISCA 2008), Beijing, China, 2008, pp. 25–36.
N. Sönmez, Cristal, A., Unsal, O., Harris, T., and Valero, M., Why you should profile Transactional Memory Applications on an Atomic Block basis: A Haskell Case Study. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, 2008.
F. Zyulkyarov, Cristal, A., Cvijic, S., Ayguadé, E., Valero, M., Unsal, O., and Harris, T., WormBench: a configurable workload for evaluating transactional memory systems, in 9th workshop on MEmory performance: DEaling with Applications, systems and architecture (MEDEA 2008), Toronto, Canada, 2008, pp. 61–68.
2007
M. Milovanovic, Unsal, O., Cristal, A., Stipić, S., Zyulkyarov, F., and Valero, M., Compile time support for using transactional memory in C/C++ applications, in The 11th Annual Workshop on the Interaction between Compilers and Computer Architecture (INTERACT-11), Phoenix, AR, United States, 2007, pp. 16–23.
C. Perfumo, Sönmez, N., Cristal, A., Unsal, O., and Valero, M., Development and Analysis of the Haskell Transactional Memory Benchmark Suite, in 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07), L'Aquila, Italy, 2007, pp. 139–140.
C. Perfumo, Sönmez, N., Unsal, O., Cristal, A., Harris, T., and Valero, M., Dissecting Transactional Executions in Haskell, in The Second ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2007), Portland, OR, United States, 2007.
E. Lara, Cristal, A., and Valero, M., El Procesador Kilo-Ruanahead, una Alternativa para Reducir el Número de Registros Físicos del Procesador Kilo-Instruction, in II Congreso Español de Informática (CEDI 2007), Zaragoza, Spain, 2007.
M. Milovanovic, Unsal, O., Cristal, A., Stipić, S., Zyulkyarov, F., and Valero, M., Extending C/C++ Language with Atomic Constructs, in II Congreso Español de Informática (CEDI 2007), Zaragoza, Spain, 2007.
M. Pericàs, Cristal, A., Cazorla, F., González, R., Jiménez, D., and Valero, M., A Flexible Heterogeneous Multi-Core Architecture, in The 2007 International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), Brasov, Romania, 2007, pp. 13–24.
S. Tomić, Cristal, A., Unsal, O., and Valero, M., Hardware Transactional Memory with Operating System Support, HTMOS, in Workshop on Highly Parallel Processing on a Chip in conjunction with Euro-Par, IRISA, Rennes, France, 2007.
M. Galluzzi, Vallejo, E., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J. E., and Valero, M., Implicit Transactional Memory in Kilo-Instruction Multiprocessor, in The Twelfth Asia-Pacific Computer Systems Architecture Conference (ACSAC 2007), Seoul, South Korea, 2007, pp. 339–353.
N. Sönmez, Perfumo, C., Stipić, S., Cristal, A., Unsal, O., and Valero, M., Increasing the Performance of Haskell Software Transactional Memory, in II Congreso Español de Informática (CEDI 2007), Zaragoza, Spain, 2007.
F. Zyulkyarov, Unsal, O., Cristal, A., Milovanovic, M., Ayguadé, E., and Valero, M., Memory Management for Transaction Processing Core in Heterogeneous Chip Multiprocessors, in Workshop on Operating System Support for Heterogeneous Multicore Architectures, Brasov, Romania, 2007.
I. González, Galluzzi, M., Cristal, A., and Valero, M., The Multi-State Processor, in 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07), L'Aquila, Italy, 2007, pp. 127–130.
I. González, Galluzzi, M., Cristal, A., and Valero, M., Multi-State Processor: Arquitectura sin ROB y con recuperaciones Precisas, in II Congreso Español de Informática (CEDI 2007), Zaragoza, Spain, 2007.
M. Milovanovic, Ferrer, R., Gajinov, V., Unsal, O., Cristal, A., Ayguadé, E., and Valero, M., Multithreaded software transactional memory and OpenMP, in 8th MEDEA Workshop Memory Performance: Dealing With Applications, Systems And Architecture (MEDEA 2007), Brasov, Romania, 2007, pp. 81–88.
A. García, Santana, O. J., Fernández, E., Medina, P., Cristal, A., and Valero, M., Reducing the Activity of Instruction Renaming in Loop Structures, in II Congreso Español de Informática (CEDI 2007), Zaragoza, Spain, 2007.
F. Zyulkyarov, Unsal, O., Cristal, A., and Valero, M., Synthetic Workloads for Transactional Memory, in 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07), L'Aquila, Italy, 2007, pp. 135–137.
T. Harris, Cristal, A., Unsal, O., Ayguadé, E., Galiardi, F., Smith, B., and Valero, M., Transactional Memory: An Overview, IEEE Micro, vol. 27, pp. 8–29, 2007.
M. Milovanovic, Ferrer, R., Unsal, O., Cristal, A., Martorell, X., Ayguadé, E., Labarta, J., and Valero, M., Transactional Memory and OpenMP, in International Workshop on OpenMP (IWOMP-2007), Beijing, China, 2007, pp. 37–53.
N. Sönmez, Perfumo, C., Stipić, S., Unsal, O., Cristal, A., and Valero, M., UnreadTVar: Extending Haskell Software Transactional Memory for Performance, in The 8th Symposium on Trends in Functional Programming (TFP 2007), New York, United States, 2007, pp. 1–11.
2006
M. Pericàs, Cristal, A., González, R., Cazorla, F., Jiménez, D. A., and Valero, M., Boosting ILP{&}TLP with the Flexible Multi-Core (FMC), in 2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06), L'Aquila, Italy, 2006, pp. 125–128.
E. Vallejo, Galluzzi, M., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J. E., and Valero, M., Chip Multiprocessors with Implicit Transactions, in 2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06), L'Aquila, Italy, 2006, pp. 167–170.
M. Pericàs, Cristal, A., González, R., Jiménez, D., and Valero, M., A decoupled KILO-instruction processor, in The 12th International Symposium on High-Performance Computer Architecture (HPCA-12), Auctin, TX, United States, 2006, pp. 53–64.
A. Cristal, Kilo Instruction Processors, Universitat Politècnica de Catalunya (UPC), 2006.
T. Ramírez, Cristal, A., Santana, O. J., Pajuelo, A., and Valero, M., Kilo-Instruction Processors, RunAhead and Prefetch, in ACM International Conference on Computing Frontiers (CF 2006), Ischia, Italy, 2006.
2005
R. González, Cristal, A., Pericàs, M., Veidenbaum, A., and Valero, M., Arquitectura Simétrica Clusterizada basada en el Contenido, in XVI Jornadas de Paralelismo, Granada, Spain, 2005.
R. González, Cristal, A., Pericàs, M., Valero, M., and Veidenbaum, A., An asymetric Clustered Processor Based on Value Content, in The 19th ACM International Conference on Supercomputing (ICS'05), Boston, MA, United States, 2005, pp. 61–70.
M. Pericàs, Cristal, A., González, R., and Valero, M., Decoupled State-Execute Architecture, in 6th International Symposium on High Performance Computing (ISHPC-VI 2005), Nara, Japan, 2005, pp. 68–78.
T. Ramírez, Galluzzi, M., Cristal, A., and Valero, M., Different approaches using Kilo-instruction Processors, in 2005 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-2005), L'Aquila, Italy, 2005.
T. Ramírez, Cristal, A., Pajuelo, A., Santana, O. J., and Valero, M., Eficacia vs. Eficiencia: Una decisión de diseño en Runahead, in XVI Jornadas de Paralelismo, Granada, Spain, 2005.
M. Pericàs, Cristal, A., González, R., Jiménez, D. A., and Valero, M., Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor, in 6th International Symposium on High Performance Computing (ISHPC-VI 2005), Nara, Japan, 2005, pp. 56–67.
E. Vallejo, Galluzzi, M., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J. E., and Valero, M., Implementing Kilo-Instruction Multiprocessors, in International Conference on Pervasive Services (ICPS 2005), Santorini, Greece, 2005, pp. 325–336.
A. Cristal, Santana, O. J., Cazorla, F., Galluzzi, M., Ramírez, T., Pericàs, M., and Valero, M., Kilo-instruction Processors: Overcoming the Memory Wall, IEEE Micro, vol. 25. pp. 48–57, 2005.
E. Vallejo, Galluzzi, M., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J. E., and Valero, M., KIMP: Multicheckpointing Multiprocessors, in XVI Jornadas de Paralelismo, Granada, Spain, 2005.
M. A. Ramírez, Cristal, A., Valero, M., Veidenbaum, A., and Villa, L. A., A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation, in IEEE International Conference on Computer Design (ICCD-2005), San José, CA, United States, 2005, pp. 647–653.
M. Pericàs, González, R., Cristal, A., and Valero, M., Overcoming the Memor Wall with D-KIPs, in 2005 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-2005), L'Aquila, Italy, 2005, pp. 99–102.
A. García, Medina, P., Fernández, E., Santana, O. J., Cristal, A., and Valero, M., Towards the Loop Processor Architecture, in XVI Jornadas de Paralelismo, Granada, Spain, 2005.

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