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Balancing HPC Applications Through Smart Allocation of Resources in MT Processors. (2008).at <http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4536293>
A Dynamic Scheduler for Balancing HPC Applications. (2008).at <http://portal.acm.org/citation.cfm?id=1413412>
Software-Controlled Priority Characterization of POWER5 Processor. (2008).at <http://www2.computer.org/portal/web/csdl/doi/10.1109/ISCA.2008.8>
CPU accounting in CMP Processors. (2009).
Analyzing OS noise for HPC systems. (2010).
A Case for Energy Aware Accounting in Large Scale Computing Facilities: Cost Metrics and Implications for Processor Design. (2010).
J-DSE: Joint Software and Hardware Design Space Exploration for Application Specific Processors. (2010).
A Case for Energy-Aware Accounting and Billing in Large-Scale Computing Facilities Cost Metrics and Design Implications. IEEE Micro (2011).
Characterizing Power and Temperature Behavior of POWER6-Based System. (invited paper). IEEE Journal of Emerging and Selected Topics in Circuits and Systems (2011).
STM2: A Parallel STM for High Performance Simultaneous Multi-Threading Systems. The 20th IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT) (2011).
Assessing the suitability of the NGMP multi-core processor in the Space domain. International Conference on Embedded Software (EMSOFT) (2012).
Characterizing Thread Placement in the IBM POWER7 Processor. IEEE International Symposium on Workload Characterization (IISWC-2013) 1–11 (2012).at <http://capinfo.e.ac.upc.edu/PDFs/dir07/file004125.pdf>
CPU Accounting for Multicore Processors. IEEE Transactions on Computers 61, 251–264 (2012).
Evaluating the impact of tlb misses on future HPC systems. The 26th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2012) (2012).
Hardware/Software Techniques for Assisted Execution Runtime Systems. The 2nd Workshop on Runtime Environments, Systems, Layering and Virtualized Environments (RESoLVE) (2012).
Making Data Prefetch Smarter: Adaptive Prefetching on POWER7. 21st International Conference on Parallel Architectures and Compilation Techniques (PACT-2012) 137–146 (2012).
SMT Malleability in IBM POWER5 and POWER6 Processors. IEEE Transactions on Computers 00, (2012).