Publications

Export 30 results:
Author Title Type [ Year(Desc)]
Filters: Author is Roberto Gioiosa  [Clear All Filters]
2008
C. Boneti, Cazorla, F., Gioiosa, R., Corbalán, J., Labarta, J., and Valero, M., Balancing HPC Applications Through Smart Allocation of Resources in MT Processors. Miami, Florida, USA, 2008.
C. Boneti, Gioiosa, R., Cazorla, F., and Valero, M., A Dynamic Scheduler for Balancing HPC Applications. Austin, USA, 2008.
P. Radojkovic, Cakarevic, V., Verdú, J., Pajuelo, A., Gioiosa, R., Cazorla, F., Nemirovsky, M., and Valero, M., Measuring Operating System Overhead on CMT Processors. In 20th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). Campo Grande, Brazil, 2008.
C. Boneti, Cazorla, F., Gioiosa, R., and Valero, M., Scheduling Real-Time Systems With Explicit Resource Allocation Processors. In International Conference on Architecture of Computing Systems (ARCS). Dresden, Germany, 2008.
C. Boneti, Cazorla, F., Gioiosa, R., Cher, C. - Y., Buyuktosunoglu, A., and Valero, M., Software-Controlled Priority Characterization of POWER5 Processor. Beijing, China, 2008.
V. Cakarevic, Radojkovic, P., Verdú, J., Pajuelo, A., Gioiosa, R., Cazorla, F., Nemirovsky, M., and Valero, M., Understanding the overhead of the spin-lock loop in CMT architectures. In Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA). Beijing, China, 2008.
2009
C. Luque, Moreto, M., Cazorla, F., Gioiosa, R., Buyuktosunoglu, A., and Valero, M., CPU accounting in CMP Processors. In IEEE Computer Architecture Letters. Volume 9, 2009.
C. Luque, Moreto, M., Cazorla, F., Gioiosa, R., Buyuktosunoglu, A., and Valero, M., ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs. In International Symposium on Parallel Architectures and Compilation Techniques, North Carolina, USA, 2009.
2010
A. Morari, Piermaria, F., Betti, E., Gioiosa, R., and Cesati, M., Analyzing OS noise for HPC systems. The 6th ACACES 2010 (Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems), 2010.
V. J. Jiménez, Cazorla, F., Gioiosa, R., Kursun, E., Isci, C., Buyuktosunoglu, A., and Valero, M., A Case for Energy Aware Accounting in Large Scale Computing Facilities: Cost Metrics and Implications for Processor Design.. Workshop on Architectural Concerns in Large Datacenters (ACLD), in conjunction with ISCA, 2010.
R. Gioiosa, McKee, S. A., and Valero, M., Designing OS for HPC Applications: Scheduling. The 2010 IEEE International Conference on Cluster Computing (CLUSTER), 2010.
C. Luque, Moreto, M., Cazorla, F., Gioiosa, R., and Valero, M., ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs. XXI Jornadas de Paralelismo, 2010.
M. Paolieri, Bonesana, I., Gioiosa, R., and Valero, M., J-DSE: Joint Software and Hardware Design Space Exploration for Application Specific Processors. Programmability Issues for Multi-Core Computers (MULTIPROG), 2010.
B. Goel, McKee, S. A., Gioiosa, R., Singh, K., Bhadauria, M., and Cesati, M., Portable, Scalable, per-Core Power Estimation for Intelligent Resource Management. Green Computing Conference, 2010 International, 2010.
K. Kedzierski, Cazorla, F., Gioiosa, R., Buyuktosunoglu, A., and Valero, M., Power and Performance Aware Reconfigurable Cache for CMPs. Workshop on Next Generation Multicore/Manycore Technologies (IFMT), in conjunction with ISCA, 2010.
V. J. Jiménez, Boneti, C., Cazorla, F., Gioiosa, R., Kursun, E., Cher, C. - Y., Isci, C., Buyuktosunoglu, A., Bose, P., and Valero, M., Power and Thermal Characterization of POWER6 System. The 19th International Conference on Parallel Architectures and Compilation Techniques (PACT), 2010.
R. Gioiosa, Towards sustainable exascale computing. The 18th IEEE/IFIP VLSI System on Chip Conference (VLSI-SoC), 2010.
V. J. Jiménez, Gioiosa, R., Kursun, E., Cazorla, F., Cher, C. - Y., Buyuktosunoglu, A., Bose, P., and Valero, M., Trends and techniques for energy efficient architectures. The 18th IEEE/IFIP VLSI System on Chip Conference (VLSI-SoC), 2010.
C. Boneti, Gioiosa, R., Cazorla, F., and Valero, M., Using hardware resource allocation to balance HPC applications, Parallel and Distributed Computing, Parallel and Distributed Computing, 2010.
2012
M. Fernández, Gioiosa, R., Quiñones, E., Fossati, L., Zulianello, M., and Cazorla, F. J., Assessing the suitability of the NGMP multi-core processor in the Space domain, International Conference on Embedded Software (EMSOFT). 2012.
S. Manousopoulos, Moretó, M., Gioiosa, R., Koziris, N., and Cazorla, F. J., Characterizing Thread Placement in the IBM POWER7 Processor, IEEE International Symposium on Workload Characterization (IISWC-2013). IEEE, San Diego, United States, pp. 1–11, 2012.
C. Luque, Moretó, M., Cazorla, F. J., Gioiosa, R., Buyuktosunoglu, A., and Valero, M., CPU Accounting for Multicore Processors, IEEE Transactions on Computers, vol. 61. pp. 251–264, 2012.
A. Morari, Gioiosa, R., Wisniewski, R. W., Rosenburg, B., Inglett, T., and Valero, M., Evaluating the impact of tlb misses on future HPC systems, The 26th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2012). IEEE, Shanghai, China, 2012.
G. Kestor, Gioiosa, R., Unsal, O., Cristal, A., and Valero, M., Hardware/Software Techniques for Assisted Execution Runtime Systems, The 2nd Workshop on Runtime Environments, Systems, Layering and Virtualized Environments (RESoLVE). 2012.
V. Jiménez, Gioiosa, R., Cazorla, F. J., Buyuktosunoglu, A., Bose, P., and O'Connell, F. P., Making Data Prefetch Smarter: Adaptive Prefetching on POWER7, 21st International Conference on Parallel Architectures and Compilation Techniques (PACT-2012). ACM, Minneapolis, United States, pp. 137–146, 2012.
A. Morari, Boneti, C., Cazorla, F. J., Gioiosa, R., Cher, C. - Y., Buyuktosunoglu, A., Bose, P., and Valero, M., SMT Malleability in IBM POWER5 and POWER6 Processors, IEEE Transactions on Computers, vol. 00. 2012.