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Morari, A., Piermaria, F., Betti, E., Gioiosa, R. & Cesati, M. Analyzing OS noise for HPC systems. (2010).
Jiménez, V. J. et al. A Case for Energy Aware Accounting in Large Scale Computing Facilities: Cost Metrics and Implications for Processor Design. (2010).
Gioiosa, R., McKee, S. A. & Valero, M. Designing OS for HPC Applications: Scheduling. (2010).
Luque, C., Moreto, M., Cazorla, F., Gioiosa, R. & Valero, M. ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs. (2010).
Paolieri, M., Bonesana, I., Gioiosa, R. & Valero, M. J-DSE: Joint Software and Hardware Design Space Exploration for Application Specific Processors. (2010).
Goel, B. et al. Portable, Scalable, per-Core Power Estimation for Intelligent Resource Management. (2010).
Kedzierski, K., Cazorla, F., Gioiosa, R., Buyuktosunoglu, A. & Valero, M. Power and Performance Aware Reconfigurable Cache for CMPs. (2010).
Jiménez, V. J. et al. Power and Thermal Characterization of POWER6 System. (2010).
Gioiosa, R. Towards sustainable exascale computing. (2010).
Jiménez, V. J. et al. Trends and techniques for energy efficient architectures. (2010).
Boneti, C., Gioiosa, R., Cazorla, F. & Valero, M. (Parallel and Distributed Computing, 2010).
Fernández, M. et al. Assessing the suitability of the NGMP multi-core processor in the Space domain. International Conference on Embedded Software (EMSOFT) (2012).
Manousopoulos, S., Moretó, M., Gioiosa, R., Koziris, N. & Cazorla, F. J. Characterizing Thread Placement in the IBM POWER7 Processor. IEEE International Symposium on Workload Characterization (IISWC-2013) 1–11 (2012). at <>
Luque, C. et al. CPU Accounting for Multicore Processors. IEEE Transactions on Computers 61, 251–264 (2012).
Morari, A. et al. Evaluating the impact of tlb misses on future HPC systems. The 26th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2012) (2012).
Kestor, G., Gioiosa, R., Unsal, O., Cristal, A. & Valero, M. Hardware/Software Techniques for Assisted Execution Runtime Systems. The 2nd Workshop on Runtime Environments, Systems, Layering and Virtualized Environments (RESoLVE) (2012).
Jiménez, V. et al. Making Data Prefetch Smarter: Adaptive Prefetching on POWER7. 21st International Conference on Parallel Architectures and Compilation Techniques (PACT-2012) 137–146 (2012).
Morari, A. et al. SMT Malleability in IBM POWER5 and POWER6 Processors. IEEE Transactions on Computers 00, (2012).