Publications

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2009
Paolieri, M., Quiñones, E., Cazorla, F. & Valero, M. An Analyzable Memory Controller for Hard Real-Time CMPs. IEEE Embedded Systems Letters 1, (2009).
Markovic, N., González, R., Unsal, O., Valero, M. & Cristal, A. Architecture for Object-Oriented Programming Model. (2009). at <http://capinfo.e.ac.upc.edu/PDFs/dir11/file003491.pdf>
Zyulkyarov, F. et al. Atomic Quake: Using Transactional Memory in an Interactive Multiplayer Game Server. 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2009) 25–34 (ACM, 2009).
Rico, A., Ramirez, A. & Valero, M. Available task-level parallelism on the Cell BE. Scientific Programming 17, 59-76 (2009).
Cakarevic, V. et al. Characterizing the resource-sharing levels in the UltraSPARC T2 Processor. (2009).
Sanyal, S., Roy, S., Cristal, A., Unsal, O. & Valero, M. Clock gate on abort: Towards energy-efficient hardware Transactional Memory. 23rd IEEE International Symposium on Parallel {&} Distributed Processing (IPDPS 2009) 1–8 (IEEE, 2009).
Luque, C. et al. CPU accounting in CMP Processors. (2009).
Santana, O. J., Falcón, A., Ramirez, A. & Valero, M. DIA: A Complexity-Effective Decoding Architecture. IEEE Transactions on Computers 58, 448-462 (2009).
Sanyal, S., Roy, S., Cristal, A., Unsal, O. & Valero, M. Dynamically Filtering Thread-Local Variables in Lazy-Lazy Hardware Transactional Memory. 11th IEEE International Conference on High Performance Computing and Communications, HPCC 2009 171–179 (IEEE, 2009).
Tomić, S. et al. EazyHTM, Eager-Lazy Hardware Transactional Memory. 42nd International Symposium on Microarchitecture (MICRO) (2009). at <http://capinfo.e.ac.upc.edu/PDFs/dir07/file003458.pdf>
Paolieri, M., Quiñones, E., Cazorla, F. & Valero, M. Efficient Execution of Mixed Application Workloads in a Hard Real-Time. (2009).
Sánchez, F., Ramirez, A. & Valero, M. Exploiting Different Levels of Parallelism in the Biological Sequence Comparison Problem. 4CCC. 4th Colombian Computing Conference (2009).
Moreto, M., Cazorla, F., Ramirez, A., Sakellariou, R. & Valero, M. FlexDCP: a QoS framework for CMP architectures. ACM SIGOPS Operating System Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors 43, 0163-5980 (2009).
Paolieri, M., Quiñones, E., Cazorla, F., Bernat, G. & Valero, M. Hardware Support for WCET Analysis of Multicore Systems. (2009).
Azevedo, A. et al. A Highly Scalable Parallel Implementation of H.264. Transactions on High-Performance Embedded Architectures and Compilers 4, (2009).
Luque, C. et al. ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs. (2009).
Azevedo, A. et al. Parallel H.264 Decoding on an Embedded Multicore Processor. 4th International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC'09) 404-418 (2009).
Álvarez, M. et al. Performance Evaluation of Macroblock-level Parallelization of H.264 Decoding on a cc-NUMA Multiprocessor Architecture. Avances en Sistemas e Informática 6, 219-228 (2009).
Sönmez, N., Cristal, A., Unsal, O., Harris, T. & Valero, M. Profiling Transactional Memory applications on an Atomic Block Basis: A Haskell case study. Second Workshop on Programmability Issues for Multi-Core Computers (MULTIPROG 2009) (2009).
Kedzierski, K., Moreto, M., Cazorla, F. & Valero, M. pseudo-LRU based Cache Partitioning Algorithms. (2009).
Gajinov, V. et al. QuakeTM: parallelizing a complex sequential application using transactional memory. 23rd international conference on Supercomputing (ICS 2009) 126–135 (ACM, 2009). at <http://capinfo.e.ac.upc.edu/PDFs/dir21/file003443.pdf>
Sánchez, F., Ramirez, A. & Valero, M. Quantitative analysis of sequence alignment applications on multiprocessor architectures. 6th ACM conference on Computing frontiers 61-70 (2009).
Kestor, G., Stipić, S., Unsal, O., Cristal, A. & Valero, M. RMS-TM: A Transactional Memory Benchmark for Recognition, Mining and Synthesis Applications. 4th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2009) (2009). at <http://capinfo.e.ac.upc.edu/PDFs/dir12/file003695.pdf>
Álvarez, M., Ramirez, A., Meenderinck, C., Juurlink, B. & Valero, M. Scalability of Macroblock-level parallelism for H.264 decoding. The Fifteenth International Conference on Parallel and Distributed Systems (ICPADS'09) (2009).
Sönmez, N. et al. Software Transactional Memory Implementation. Advanced Computer Architecture and Computation for Embedded Systems (ACACES 2009) 101–103 (Academia Press, 2009).
Sonmez, N., Harris, T., Cristal, A., Unsal, O. & Valero, M. Taking the heat off transactions: Dynamic selection of pessimistic concurrency control. Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing 1–10 (2009). doi:10.1109/IPDPS.2009.5161032
Sönmez, N., Harris, T., Cristal, A., Unsal, O. & Valero, M. Taking the heat off transactions: Dynamic selection of pessimistic concurrency control. 23rd IEEE International Symposium on Parallel {&} Distributed Processing (IPDPS 2009) 1–10 (IEEE, 2009).
Acosta, C., Cazorla, F., Ramirez, A. & Valero, M. Thread to Core Assignment in SMT On-Chip Multiprocessors. 21st International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'09) (2009).
Kulkarni, C., Unsal, O., Cristal, A., Ayguadé, E. & Valero, M. Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions. ACM SIGPLAN Notices 44, 307–308 (2009).
Kulkarni, C., Unsal, O., Cristal, A., Ayguadé, E. & Valero, M. Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions. 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2009) 307–308 (ACM, 2009).
2008
Vega, A., Ramirez, A. & Valero, M. 3D Die-Stacking Architectures: State of the Art. Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008 203-207 (2008).
Castillo, P. A. et al. Architecture performance prediction using evolutionary artificial neural networks. (2008).
Boneti, C. et al. Balancing HPC Applications Through Smart Allocation of Resources in MT Processors. (2008). at <http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4536293>
González, I. et al. A distributed processor state management architecture for large-window processors. 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41) 11–22 (IEEE Computer Society, 2008). at <http://capinfo.e.ac.upc.edu/PDFs/dir14/file003697.pdf>
González, I. et al. A Distributed Processor State Management Architecture for Large-Window Processors. (2008).
González, I. et al. A distributed processor state management architecture for large-window processors. 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41) 11–22 (IEEE Computer Society, 2008). at <http://capinfo.e.ac.upc.edu/PDFs/dir14/file003697.pdf>
Moreto, M., Cazorla, F., Ramirez, A. & Valero, M. Dynamic Cache Partitioning Based on the MLP on Cache Misses. Transactions on HiPEAC 3, 1-21 (2008).
Boneti, C., Gioiosa, R., Cazorla, F. & Valero, M. A Dynamic Scheduler for Balancing HPC Applications. (2008). at <http://portal.acm.org/citation.cfm?id=1413412>
Castillo, P. A. et al. Evolutionary system for prediction and optimization of hardware architecture performance. (2008).
Vallejo, E., Harris, T., Cristal, A., Unsal, O. & Valero, M. Hybrid Transactional Memory to accelerate safe lock-based transactions. 3rd ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2008) (2008). at <http://capinfo.e.ac.upc.edu/PDFs/dir16/file003699.pdf>
Perfumo, C. et al. The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment. Computing Frontiers '08 67–78 (2008).
Perfumo, C. et al. The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment. 5th Conference on Computing Frontiers 67–78 (ACM, 2008). at <http://capinfo.e.ac.upc.edu/PDFs/dir06/file003457.pdf>
Radojkovic, P. et al. Measuring Operating System Overhead on CMT Processors. (2008).
Acosta, C., Cazorla, F., Ramirez, A. & Valero, M. MFLUSH: Handling Long-latency loads in SMT On-Chip Multiprocessors. International Conference on Parallel Processing (ICPP) 173-181 (2008).
Moreto, M., Cazorla, F., Ramirez, A. & Valero, M. MLP-aware dynamic cache partitioning. 2008 International Conference on High Performance Embedded Architectures & Compilers (HiPEAC 2008) 337-352 (2008).
Nesbit, K. J. et al. Multicore Resource Management. IEEE Micro 28, 6-16 (2008).
Milovanovic, M. et al. Nebelung: Execution Environment for Transactional OpenMP. International Journal of Parallel Programming 36, 326–346 (2008).
Sánchez, F., Ramirez, A. & Valero, M. Parallelization Strategies for Smith Waterman Algorithm on CellBE. Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008, Poster Session (2008).
Isaza, S., Sánchez, F., Gaydadjiev, G. N., Ramirez, A. & Valero, M. Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications. Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS'08) 53-64 (2008).
Álvarez, M., Ramirez, A., Martorell, X., Ayguadé, E. & Valero, M. Scalability of Macroblock-level Parallelism for H.264 Decoding. Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008, Poster 59-62 (2008).

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