Publications

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2010
A. Vega, Rico, A., Cabarcas, F., Ramirez, A., and Valero, M., Comparing last-level cache designs for CMP architectures, IFMT '10: International Forum on Next-Generation Multicore/Manycore Technologies. 2010.
F. Zyulkyarov, Harris, T., Unsal, O., Cristal, A., and Valero, M., Debugging Programs that use Atomic Blocks and Transactional Memory, in 15th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming (PPoPP 2010), Bangalore, India, 2010.
R. Gioiosa, McKee, S. A., and Valero, M., Designing OS for HPC Applications: Scheduling. The 2010 IEEE International Conference on Cluster Computing (CLUSTER), 2010.
V. Marjanovic, Labarta, J., Ayguadé, E., and Valero, M., Effective Communication and Computation Overlap with Hybrid MPI/SMPSs. 15th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming (PPoPP), 2010.
M. Moreto, Cazorla, F., Ramirez, A., Sakellariou, R., and Valero, M., FlexDCP: a QoS framework for CMP architectures, ACM Operating Systems Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors, vol. 43, no. 2. pp. 86-96, 2010.
M. Moreto, Paolieri, M., Abella, J., Quiñones, E., Cazorla, F., and Valero, M., Hard Real-Time Capable Multicore Processors for Space Applications. ESTEC 1st Networking/Partnering Day, 2010.
C. Luque, Moreto, M., Cazorla, F., Gioiosa, R., and Valero, M., ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs. XXI Jornadas de Paralelismo, 2010.
M. Paolieri, Bonesana, I., Gioiosa, R., and Valero, M., J-DSE: Joint Software and Hardware Design Space Exploration for Application Specific Processors. Programmability Issues for Multi-Core Computers (MULTIPROG), 2010.
M. Moreto, Cazorla, F., Sakellariou, R., and Valero, M., Load Balancing Using Dynamic Cache Allocation. ACM International Conference on Computing Frontiers (CF), 2010.
F. Sánchez, Cabarcas, F., Ramirez, A., and Valero, M., Long DNA Sequence Comparison on Multicore Architectures, 16th international Euro-Par conference on Parallel processing. 2010.
M. Etinski, Corbalán, J., Labarta, J., and Valero, M., Optimizing Job Performance Under a Given Power Constraint In HPC Centers. International Green Computing Conference, 2010.
V. Marjanovic, Labarta, J., Ayguadé, E., and Valero, M., Overlapping Communication and Computation by Using a Hybrid MPI/SMPSs Approach. 24th International Conference on Supercomputing. Epochal Tsukuba, Tsukuba, Japan, 2010.
M. Álvarez, Ramirez, A., Valero, M., Azevedo, A., Meenderinck, C., and Juurlink, B., Performance Evaluation of Macroblock-level Parallelization of H.264 Decoding on a cc-NUMA Multiprocessor Architecture, 4CCC. 4th Colombian Computing Conference, Bucaramanga (Colombia). 2010.
K. Kedzierski, Cazorla, F., Gioiosa, R., Buyuktosunoglu, A., and Valero, M., Power and Performance Aware Reconfigurable Cache for CMPs. Workshop on Next Generation Multicore/Manycore Technologies (IFMT), in conjunction with ISCA, 2010.
V. J. Jiménez, Boneti, C., Cazorla, F., Gioiosa, R., Kursun, E., Cher, C. - Y., Isci, C., Buyuktosunoglu, A., Bose, P., and Valero, M., Power and Thermal Characterization of POWER6 System. The 19th International Conference on Parallel Architectures and Compilation Techniques (PACT), 2010.
F. Cazorla, Pajuelo, A., Santana, O. J., Fernandez, E., and Valero, M., On the Problem of Evaluating the Performance of Multiprogrammed Workloads. , IEEE Transactions on Computers, vol. 59, no. 12. IEEE, 2010.
V. Karakostas, Kestor, G., Unsal, O., Cristal, A., Hur, I., and Valero, M., RMS-TM: A challenging transactional memory benchmark suite, in Advanced Computer Architecture and Computation for Embedded Systems (ACACES 2010), Terrassa, Spain, 2010.
S. Isaza, Sánchez, F., Gaydadjiev, G. N., Ramirez, A., and Valero, M., Scalability Analysis of Progressive Alignment in a Multicore, International Workshop on Multi-Core Computing Systems (MuCoCoS 2010). Krakow (Poland), 2010.
S. Isaza, Sánchez, F., Gaydadjiev, G. N., Ramirez, A., and Valero, M., Scalability Analysis of Progressive Alignment on a Multicore, Fourth International Conference on Complex, Intelligent and Software Intensive Systems (CISIS '10). pp. 889-894, 2010.
A. Armejach, Seyedi, A., Gil, R. T. J., Hur, I., Unsal, O., Cristal, A., and Valero, M., ShadowHTM: Using a dual-bitcell L1 Data Cache to Improve Hardware Transactional Memory Performance. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, 2010.
V. Subotic, Sancho, J. C., Labarta, J., and Valero, M., A Simulation Framework to Automatically Analyze the Communication-Computation Overlap in Scientific Applications, Cluster Computing (CLUSTER), 2010 IEEE International Conference on. pp. 275-283, 2010.
Y. Etsion, Cabarcas, F., Rico, A., Ramirez, A., Badia, R. M., Ayguadé, E., Labarta, J., and Valero, M., Task Superscalar: An Out-of-Order Task Pipeline, IEEE/ACM Intl. Symp. on Microarchitecture (MICRO-43). pp. 89-100, 2010.
Y. Etsion, Ramirez, A., Badia, R. M., Ayguadé, E., Labarta, J., and Valero, M., Task Superscalar: Using Processors as Functional Units, USENIX Workshop on Hot Topics In Parallelism (HotPar). 2010.
P. Radojkovic, Cakarevic, V., Verdú, J., Pajuelo, A., Cazorla, F., Nemirovsky, M., and Valero, M., Thread to Strand Binding of Parallel Network Applications in Massive Multi-Threaded Systems. In 15th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming, Bangalore, India, 2010.
N. Miletić, Smiljkovic, V., Perfumo, C., Harris, T., Cristal, A., Hur, I., Unsal, O., and Valero, M., Transactification of a real-world system library, 5th ACM SIGPLAN Workshop on Transactional Computing - TRANSACT 2010. Paris, France, 2010.
V. J. Jiménez, Gioiosa, R., Kursun, E., Cazorla, F., Cher, C. - Y., Buyuktosunoglu, A., Bose, P., and Valero, M., Trends and techniques for energy efficient architectures. The 18th IEEE/IFIP VLSI System on Chip Conference (VLSI-SoC), 2010.
C. Boneti, Gioiosa, R., Cazorla, F., and Valero, M., Using hardware resource allocation to balance HPC applications, Parallel and Distributed Computing, Parallel and Distributed Computing, 2010.
M. Etinski, Corbalán, J., Labarta, J., and Valero, M., Utilization Driven Power-Aware Job Scheduling. Computer Science - Research and Development, Volume 25, Number 3-4, 2010.
2009
M. Paolieri, Quiñones, E., Cazorla, F., and Valero, M., An Analyzable Memory Controller for Hard Real-Time CMPs, IEEE Embedded Systems Letters, vol. 1, no. 4. 2009.
N. Markovic, González, R., Unsal, O., Valero, M., and Cristal, A., Architecture for Object-Oriented Programming Model. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, 2009.
F. Zyulkyarov, Gajinov, V., Unsal, O., Cristal, A., Ayguadé, E., Harris, T., and Valero, M., Atomic Quake: Using Transactional Memory in an Interactive Multiplayer Game Server, in 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2009), Raleigh, North Carolina, United States, 2009, pp. 25–34.
A. Rico, Ramirez, A., and Valero, M., Available task-level parallelism on the Cell BE, Scientific Programming, vol. 17, no. 1-2. pp. 59-76, 2009.
V. Cakarevic, Radojkovic, P., Verdú, J., Pajuelo, A., Cazorla, F., Nemirovsky, M., and Valero, M., Characterizing the resource-sharing levels in the UltraSPARC T2 Processor. In 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), New York, USA, 2009.
S. Sanyal, Roy, S., Cristal, A., Unsal, O., and Valero, M., Clock gate on abort: Towards energy-efficient hardware Transactional Memory, in 23rd IEEE International Symposium on Parallel {&} Distributed Processing (IPDPS 2009), Rome, Italy, 2009, pp. 1–8.
C. Luque, Moreto, M., Cazorla, F., Gioiosa, R., Buyuktosunoglu, A., and Valero, M., CPU accounting in CMP Processors. In IEEE Computer Architecture Letters. Volume 9, 2009.
O. J. Santana, Falcón, A., Ramirez, A., and Valero, M., DIA: A Complexity-Effective Decoding Architecture, IEEE Transactions on Computers, vol. 58, no. 4. pp. 448-462, 2009.
S. Sanyal, Roy, S., Cristal, A., Unsal, O., and Valero, M., Dynamically Filtering Thread-Local Variables in Lazy-Lazy Hardware Transactional Memory, in 11th IEEE International Conference on High Performance Computing and Communications, HPCC 2009, Seoul, South Korea, 2009, pp. 171–179.
S. Tomić, Perfumo, C., Kulkarni, C., Armejach, A., Cristal, A., Unsal, O., Harris, T., and Valero, M., EazyHTM, Eager-Lazy Hardware Transactional Memory, in 42nd International Symposium on Microarchitecture (MICRO), New York, United States, 2009.
M. Paolieri, Quiñones, E., Cazorla, F., and Valero, M., Efficient Execution of Mixed Application Workloads in a Hard Real-Time. In Workshop on Reconciling Performance with Predictability (RePP) Oct. 15, 2009, during the ESWEEK, Grenoble, France, 2009.
F. Sánchez, Ramirez, A., and Valero, M., Exploiting Different Levels of Parallelism in the Biological Sequence Comparison Problem, 4CCC. 4th Colombian Computing Conference. Bucaramanga (Colombia), 2009.
M. Moreto, Cazorla, F., Ramirez, A., Sakellariou, R., and Valero, M., FlexDCP: a QoS framework for CMP architectures, ACM SIGOPS Operating System Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors, vol. 43, no. 2. pp. 0163-5980, 2009.
M. Paolieri, Quiñones, E., Cazorla, F., Bernat, G., and Valero, M., Hardware Support for WCET Analysis of Multicore Systems. In International Symposium on Computer Architecture, Austin, USA, 2009.
A. Azevedo, Meenderinck, C., Juurlink, B., Tereckho, A., Hoogerbrugge, J., Álvarez, M., Ramirez, A., and Valero, M., A Highly Scalable Parallel Implementation of H.264, Transactions on High-Performance Embedded Architectures and Compilers, vol. 4, no. 2. 2009.
C. Luque, Moreto, M., Cazorla, F., Gioiosa, R., Buyuktosunoglu, A., and Valero, M., ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs. In International Symposium on Parallel Architectures and Compilation Techniques, North Carolina, USA, 2009.
A. Azevedo, Meenderinck, C., Juurlink, B., Terechko, A., Hoogerbrugge, J., Álvarez, M., Ramirez, A., and Valero, M., Parallel H.264 Decoding on an Embedded Multicore Processor, 4th International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC'09). pp. 404-418, 2009.
M. Álvarez, Ramirez, A., Valero, M., Azevedo, A., Meenderinck, C., and Juurlink, B., Performance Evaluation of Macroblock-level Parallelization of H.264 Decoding on a cc-NUMA Multiprocessor Architecture, Avances en Sistemas e Informática, vol. 6, no. 1. pp. 219-228, 2009.
N. Sönmez, Cristal, A., Unsal, O., Harris, T., and Valero, M., Profiling Transactional Memory applications on an Atomic Block Basis: A Haskell case study, in Second Workshop on Programmability Issues for Multi-Core Computers (MULTIPROG 2009), Paphos, Cyprus, 2009.
K. Kedzierski, Moreto, M., Cazorla, F., and Valero, M., pseudo-LRU based Cache Partitioning Algorithms. In International Symposium on Parallel Architectures and Compilation Techniques, North Carolina, USA, 2009.
V. Gajinov, Zyulkyarov, F., Unsal, O. S., Cristal, A., Ayguadé, E., Harris, T., and Valero, M., QuakeTM: parallelizing a complex sequential application using transactional memory, Proceedings of the 23rd international conference on Supercomputing. ACM, pp. 126–135, 2009.
V. Gajinov, Zyulkyarov, F., Unsal, O., Cristal, A., Ayguadé, E., Harris, T., and Valero, M., QuakeTM: parallelizing a complex sequential application using transactional memory, in 23rd international conference on Supercomputing (ICS 2009), Yorktown Heights, NY, United States, 2009, pp. 126–135.

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