Publications

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2009
Azevedo, A., Meenderinck, C., Juurlink, B., Tereckho, A., Hoogerbrugge, J., Álvarez, M., Ramirez, A. & Valero, M. A Highly Scalable Parallel Implementation of H.264. Transactions on High-Performance Embedded Architectures and Compilers 4, (2009).
Luque, C., Moreto, M., Cazorla, F., Gioiosa, R., Buyuktosunoglu, A. & Valero, M. ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs. (2009).
Azevedo, A., Meenderinck, C., Juurlink, B., Terechko, A., Hoogerbrugge, J., Álvarez, M., Ramirez, A. & Valero, M. Parallel H.264 Decoding on an Embedded Multicore Processor. 4th International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC'09) 404-418 (2009).
Álvarez, M., Ramirez, A., Valero, M., Azevedo, A., Meenderinck, C. & Juurlink, B. Performance Evaluation of Macroblock-level Parallelization of H.264 Decoding on a cc-NUMA Multiprocessor Architecture. Avances en Sistemas e Informática 6, 219-228 (2009).
Sönmez, N., Cristal, A., Unsal, O., Harris, T. & Valero, M. Profiling Transactional Memory applications on an Atomic Block Basis: A Haskell case study. Second Workshop on Programmability Issues for Multi-Core Computers (MULTIPROG 2009) (2009).
Kedzierski, K., Moreto, M., Cazorla, F. & Valero, M. pseudo-LRU based Cache Partitioning Algorithms. (2009).
Gajinov, V., Zyulkyarov, F., Unsal, O., Cristal, A., Ayguadé, E., Harris, T. & Valero, M. QuakeTM: parallelizing a complex sequential application using transactional memory. 23rd international conference on Supercomputing (ICS 2009) 126–135 (2009).at <http://capinfo.e.ac.upc.edu/PDFs/dir21/file003443.pdf>
Sánchez, F., Ramirez, A. & Valero, M. Quantitative analysis of sequence alignment applications on multiprocessor architectures. 6th ACM conference on Computing frontiers 61-70 (2009).
Kestor, G., Stipić, S., Unsal, O., Cristal, A. & Valero, M. RMS-TM: A Transactional Memory Benchmark for Recognition, Mining and Synthesis Applications. 4th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2009) (2009).at <http://capinfo.e.ac.upc.edu/PDFs/dir12/file003695.pdf>
Álvarez, M., Ramirez, A., Meenderinck, C., Juurlink, B. & Valero, M. Scalability of Macroblock-level parallelism for H.264 decoding. The Fifteenth International Conference on Parallel and Distributed Systems (ICPADS'09) (2009).
Sönmez, N., Perfumo, C., Stipić, S., Harris, T., Unsal, O., Cristal, A. & Valero, M. Software Transactional Memory Implementation. Advanced Computer Architecture and Computation for Embedded Systems (ACACES 2009) 101–103 (2009).
Sonmez, N., Harris, T., Cristal, A., Unsal, O. & Valero, M. Taking the heat off transactions: Dynamic selection of pessimistic concurrency control. Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing 1–10 (2009).doi:10.1109/IPDPS.2009.5161032
Sönmez, N., Harris, T., Cristal, A., Unsal, O. & Valero, M. Taking the heat off transactions: Dynamic selection of pessimistic concurrency control. 23rd IEEE International Symposium on Parallel {&} Distributed Processing (IPDPS 2009) 1–10 (2009).
Acosta, C., Cazorla, F., Ramirez, A. & Valero, M. Thread to Core Assignment in SMT On-Chip Multiprocessors. 21st International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'09) (2009).
Kulkarni, C., Unsal, O., Cristal, A., Ayguadé, E. & Valero, M. Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions. ACM SIGPLAN Notices 44, 307–308 (2009).
Kulkarni, C., Unsal, O., Cristal, A., Ayguadé, E. & Valero, M. Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions. 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2009) 307–308 (2009).
2008
Vega, A., Ramirez, A. & Valero, M. 3D Die-Stacking Architectures: State of the Art. Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008 203-207 (2008).
Castillo, P.A., Mora, A.M., Merelo, J.J., Laredo, J.L., Moreto, M., Cazorla, F., Valero, M. & McKee, S.A. Architecture performance prediction using evolutionary artificial neural networks. (2008).
Boneti, C., Cazorla, F., Gioiosa, R., Corbalán, J., Labarta, J. & Valero, M. Balancing HPC Applications Through Smart Allocation of Resources in MT Processors. (2008).at <http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4536293>
González, I., Galluzzi, M., Veidenbaum, A., Ramirez, A., Cristal, A. & Valero, M. A distributed processor state management architecture for large-window processors. 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41) 11–22 (2008).at <http://capinfo.e.ac.upc.edu/PDFs/dir14/file003697.pdf>
González, I., Galluzzi, M., Veidenbaum, A., Ramírez, M.A., Cristal, A. & Valero, M. A Distributed Processor State Management Architecture for Large-Window Processors. (2008).
González, I., Galluzzi, M., Veidenbaum, A., Ramírez, M.A., Cristal, A. & Valero, M. A distributed processor state management architecture for large-window processors. 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41) 11–22 (2008).at <http://capinfo.e.ac.upc.edu/PDFs/dir14/file003697.pdf>
Moreto, M., Cazorla, F., Ramirez, A. & Valero, M. Dynamic Cache Partitioning Based on the MLP on Cache Misses. Transactions on HiPEAC 3, 1-21 (2008).
Boneti, C., Gioiosa, R., Cazorla, F. & Valero, M. A Dynamic Scheduler for Balancing HPC Applications. (2008).at <http://portal.acm.org/citation.cfm?id=1413412>
Castillo, P.A., Merelo, J.J., Moreto, M., Cazorla, F., Valero, M., Mora, A.M., Laredo, J.L. & McKee, S.A. Evolutionary system for prediction and optimization of hardware architecture performance. (2008).
Vallejo, E., Harris, T., Cristal, A., Unsal, O. & Valero, M. Hybrid Transactional Memory to accelerate safe lock-based transactions. 3rd ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2008) (2008).at <http://capinfo.e.ac.upc.edu/PDFs/dir16/file003699.pdf>
Perfumo, C., Sönmez, N., Stipić, S., Unsal, O., Cristal, A., Harris, T. & Valero, M. The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment. 5th Conference on Computing Frontiers 67–78 (2008).at <http://capinfo.e.ac.upc.edu/PDFs/dir06/file003457.pdf>
Perfumo, C., Sönmez, N., Stipic, S., Unsal, O., Cristal, A., Harris, T. & Valero, M. The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment. Computing Frontiers '08 67–78 (2008).
Radojkovic, P., Cakarevic, V., Verdú, J., Pajuelo, A., Gioiosa, R., Cazorla, F., Nemirovsky, M. & Valero, M. Measuring Operating System Overhead on CMT Processors. (2008).
Acosta, C., Cazorla, F., Ramirez, A. & Valero, M. MFLUSH: Handling Long-latency loads in SMT On-Chip Multiprocessors. International Conference on Parallel Processing (ICPP) 173-181 (2008).
Moreto, M., Cazorla, F., Ramirez, A. & Valero, M. MLP-aware dynamic cache partitioning. 2008 International Conference on High Performance Embedded Architectures & Compilers (HiPEAC 2008) 337-352 (2008).
Nesbit, K.J., Moreto, M., Cazorla, F., Ramirez, A., Valero, M. & Smith, J.E. Multicore Resource Management. IEEE Micro 28, 6-16 (2008).
Milovanovic, M., Ferrer, R., Gajinov, V., Unsal, O., Cristal, A., Ayguadé, E. & Valero, M. Nebelung: Execution Environment for Transactional OpenMP. International Journal of Parallel Programming 36, 326–346 (2008).
Sánchez, F., Ramirez, A. & Valero, M. Parallelization Strategies for Smith Waterman Algorithm on CellBE. Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008, Poster Session (2008).
Isaza, S., Sánchez, F., Gaydadjiev, G.N., Ramirez, A. & Valero, M. Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications. Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS'08) 53-64 (2008).
Álvarez, M., Ramirez, A., Martorell, X., Ayguadé, E. & Valero, M. Scalability of Macroblock-level Parallelism for H.264 Decoding. Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008, Poster 59-62 (2008).
Boneti, C., Cazorla, F., Gioiosa, R. & Valero, M. Scheduling Real-Time Systems With Explicit Resource Allocation Processors. (2008).
Alastruey, J.J., Cazorla, F., Monreal, T., Viñals, V. & Valero, M. Selection of the Register File Size and the Resource Allocation Policy on SMT Processors. (2008).
Boneti, C., Cazorla, F., Gioiosa, R., Cher, C.-Y., Buyuktosunoglu, A. & Valero, M. Software-Controlled Priority Characterization of POWER5 Processor. (2008).at <http://www2.computer.org/portal/web/csdl/doi/10.1109/ISCA.2008.8>
Rico, A., Ramirez, A. & Valero, M. Task Management Analysis on the Cell BE. XIX Jornadas de Paralelismo, pp. 271-276, Castellón (Spain) 271-276 (2008).
Vallejo, E., Sanyal, S., Harris, T., Vallejo, F., Beivide, R., Unsal, O., Cristal, A. & Valero, M. Towards Fair Scalable Locking. Workshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods (EPHAM 2008) (2008).at <http://capinfo.e.ac.upc.edu/PDFs/dir22/file003705.pdf>
Kestor, G., Unsal, O., Cristal, A. & Valero, M. Transactional Look-based Parallel Program. Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008 71–75 (2008).
Pericàs, M., Cristal, A., Cazorla, F., González, R., Veidenbaum, A., Jiménez, D.A. & Valero, M. A Two-Level Load/Store Queue Based on Execution Locality. The 35th International Symposium on Computer Architecture (ISCA 2008) 25–36 (2008).at <http://capinfo.e.ac.upc.edu/PDFs/dir05/file003514.pdf>
Pericas, M., González, R., Cazorla, F., Cristal, A., Veidenbaum, A., Jiménez, D.A. & Valero, M. A two-level Load/Store Queue based on Execution Locality. (2008).
Cakarevic, V., Radojkovic, P., Verdú, J., Pajuelo, A., Gioiosa, R., Cazorla, F., Nemirovsky, M. & Valero, M. Understanding the overhead of the spin-lock loop in CMT architectures. (2008).
Pericas, M., Chaves, R., Gaydadjiev, G.N., Valero, M. & Vassiliadis, S. Vectorized AES Core for high-throughput secure environments. (2008).
Nesbit, K.J., Moreto, M., Cazorla, F., Ramirez, A., Valero, M. & Smith, J.E. Virtual Private Machines: Hardware/Software Interactions in the Multicore Era. (2008).
Sönmez, N., Cristal, A., Unsal, O., Harris, T. & Valero, M. Why you should profile Transactional Memory Applications on an Atomic Block basis: A Haskell Case Study. (2008).
Zyulkyarov, F., Cristal, A., Cvijic, S., Ayguadé, E., Valero, M., Unsal, O. & Harris, T. WormBench: a configurable workload for evaluating transactional memory systems. 9th workshop on MEmory performance: DEaling with Applications, systems and architecture (MEDEA 2008) 61–68 (2008).at <http://capinfo.e.ac.upc.edu/PDFs/dir21/file003646.pdf>
2007
Milovanovic, M., Unsal, O., Cristal, A., Stipić, S., Zyulkyarov, F. & Valero, M. Compile time support for using transactional memory in C/C++ applications. The 11th Annual Workshop on the Interaction between Compilers and Computer Architecture (INTERACT-11) 16–23 (2007).at <http://capinfo.e.ac.upc.edu/PDFs/dir10/file003751.pdf>

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