Publications

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2016
D. Chasapis, Casas, M., Moreto, M., Vidal, R., Ayguadé, E., Labarta, J., and Valero, M., PARSECSs: Evaluating the Impact of Task Parallelism in the PARSEC Benchmark Suite, Transactions on Architecture and Code Optimization (TACO), vol. 12, no. 4. ACM, 2016.
D. Chasapis, Schulz, M., Casas, M., Ayguadé, E., Valero, M., Moreto, M., and Labarta, J., Runtime-Guided Mitigation of Manufacturing Variability in Power-Constrained Multi-Socket NUMA Nodes, Proceedings of the 2016 International Conference on Supercomputing, ICS 2016, Istanbul, Turkey, June 1-3, 2016. 2016.
T. Grass, Rico, A., Casas, M., Moreto, M., and Ayguadé, E., TaskPoint: Sampled simulation of task-based programs, 2016 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2016, Uppsala, Sweden, April 17-19, 2016. pp. 296–306, 2016.
2015
D. Prat, Ortega, C., Casas, M., Moreto, M., and Valero, M., Adaptive and application dependent runtime guided hardware prefetcher reconfiguration on the IBM POWER7, 6th International Workshop on Adaptive Self-tuning Computing Systems. arXiv.org, Amsterdam, Netherlands, pp. 1–6, 2015.
L. Álvarez, Vilanova, L., Moreto, M., Casas, M., González, M., Martorell, X., Navarro, N., Ayguadé, E., and Valero, M., Coherence Protocol for Transparent Management of Scratchpad Memories in Shared Memory Manycore Architectures, Proceedings of the 42nd International Symposium on Computer Architecture (ISCA). ACM, New York, NY, USA, pp. 720-732, 2015.
R. Vidal, Casas, M., Moreto, M., Chasapis, D., Ferrer, R., Martorell, X., Ayguadé, E., Labarta, J., and Valero, M., Evaluating the Impact of OpenMP 4.0 Extensions on Relevant Parallel Workloads, International Workshop on OpenMP (IWOMP) , no. Lecture Notes in Computer Science. LNCS, pp. 60-72, 2015.
M. Casas and Bronevetsky, G., Evaluation of HPC applications Memory Resource Consumption via Active Measurement, IEEE Transactions on Parallel and Distributed Systems (TPDS). 2015.
L. Jaulmes, Casas, M., Moreto, M., Ayguadé, E., Labarta, J., and Valero, M., Exploiting Asynchrony from Exact Forward Recovery for DUE in Iterative Solvers, SC'15 - Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis. ACM, New York, NY, USA, pp. 53:1–53:12, 2015.
S. Chen, Bronevetsky, G., Li, B., Casas, M., and Peng, L., A framework for evaluating comprehensive fault resilience mechanisms in numerical programs, The Journal of Supercomputing, vol. 71, no. 8. Springer US, pp. 2963-2984, 2015.
M. Casas, Moreto, M., Álvarez, L., Castillo, E., Chasapis, D., Hayes, T., Jaulmes, L., Palomar, O., Ünsal, O. S., Cristal, A., Ayguadé, E., Labarta, J., and Valero, M., Runtime-Aware Architectures, Euro-Par 2015: Parallel Processing, vol. 9233, no. Lecture Notes in Computer Science. pp. 16-27, 2015.
L. Álvarez, Moreto, M., Casas, M., Castillo, E., Martorell, X., Labarta, J., Ayguadé, E., and Valero, M., Runtime-Guided Management of Scratchpad Memories in Multicore Architectures, 2015 International Conference on Parallel Architecture and Compilation (PACT) . pp. 379-391, 2015.
2014
M. Casas and Bronevetsky, G., Active Measurement of Memory Resource Consumption, 28th IEEE International Parallel & Distributed Processing Symposium (IPDPS) . 2014.
M. Casas and Bronevetsky, G., Active Measurement of the Impact of Network Switch Utilization on Application Performance, 28th IEEE International Parallel & Distributed Processing Symposium (IPDPS). 2014.
T. Grass, Rico, A., Casas, M., Moreto, M., and Ramirez, A., Evaluating Execution Time Predictability of Task-Based Programs, 7th International Workshop on Multi-/Many-Core Computing Systems. Springer International Publishing, Porto, Portugal, pp. 218–229, 2014.
D. Roca, Nemirovsky, M., Moreto, M., and Casas, M., High level queuing architecture model for high-end processors. 2014.
M. Valero, Moreto, M., Casas, M., Ayguadé, E., and Labarta, J., Runtime-Aware Architectures: A First Approach, International Journal on Supercomputing Frontiers and Innovations, vol. 1. pp. 29-44, 2014.
T. Grass, Rico, A., Casas, M., Moreto, M., and Ramirez, A., Task Sampling: Computer Architecture Simulation in the Many-Core Era, Advanced Computer Architecture and Compilation for for High-Performance and Embedded Systems. Academic Press Ghent (Belgium), Fiuggi, Italy, pp. 165–168, 2014.
2011
M. Casas, Servat, H., Badia, R. M., and Labarta, J., Extracting the optimal sampling frequency of applications using spectral analysis, Concurrency and Computation: Practice and Experience. John Wiley & Sons, Ltd, p. n/a–n/a, 2011.
J. González, Giménez, J., Casas, M., Moretó, M., Ramirez, A., Labarta, J., and Valero, M., Simulating Whole Supercomputer Applications, IEEE Micro, vol. 31. IEEE, pp. 32-45, 2011.
G. Llort, Casas, M., Servat, H., Huck, K., Giménez, J., and Labarta, J., Trace Spectral Analysis toward Dynamic Levels of Detail, 17th IEEE International Conference on Parallel and Distributed Systems, ICPADS 2011, Tainan, Taiwan. pp. 332 - 339, 2011.
2010
M. Casas, Badia, R. M., and Labarta, J., Automatic Phase Detection and Structure Extraction of MPI Applications. International Journal of High Performance Computing Applications, Vol. 24, Number 3, pp. 335-360, 2010.
2008
M. Casas, Badia, R. M., and Labarta, J., Automatic analysis of speedup of MPI applications, ICS '08 Proceedings of the 22nd annual international conference on Supercomputing . International Conference on Supercomputing 2008 ( ICS 2008), 2008.
M. Casas, Badia, R. M., and Labarta, J., Prediction of Behavior of MPI Applications. IEEE Cluster 2008, 2008.