Publications

Export 135 results:
Sort by: Author [ Title (Asc)] Type Year
Filters: Author is Adrián Cristal  [Clear All Filters]
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 
S
Ramírez, M.A., Cristal, A., Veidenbaum, A., Villa, L.A. & Valero, M. A Simple Low-Energy Instruction Wakeup Mechanism. 5th International Symposium on High Performance Computing (ISHPC-V) 99–112 (2003).
Cristal, A. Síntesis de Redes de Petri. (1996).
Sönmez, N., Perfumo, C., Stipić, S., Harris, T., Unsal, O., Cristal, A. & Valero, M. Software Transactional Memory Implementation. Advanced Computer Architecture and Computation for Embedded Systems (ACACES 2009) 101–103 (2009).
Kestor, G., Gioiosa, R., Harris, T., Cristal, A., Unsal, O., Valero, M. & Hur, I. STM2: A Parallel STM for High Performance Simultaneous Multi-Threading Systems. The 20th IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT) (2011).
Gajinov, V., Stipić, S., Unsal, O.S., Harris, T., Ayguadé, E. & Cristal, A. Supporting Stateful Tasks in a Dataflow Graph. Proceedings of the 21st international conference on Parallel architectures and compilation techniques 435–436 (2012).
Yalcin, G., Unsal, O., Cristal, A., Hur, I. & Valero, M. SymptomTM: Symptom Based Error Detection and Recovery Using Hardware Transactional Memory. Parallel Architectures and Compilation Techniques (PACT) 199–200 (2011).
Zyulkyarov, F., Unsal, O., Cristal, A. & Valero, M. Synthetic Workloads for Transactional Memory. 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07) 135–137 (2007).
T
Stipić, S., Tomić, S., Zyulkyarov, F., Cristal, A., Ünsal, O.S. & Valero, M. TagTM - accelerating STMs with hardware tags for fast meta-data access. DATE 39-44 (2012).
Sönmez, N., Harris, T., Cristal, A., Unsal, O. & Valero, M. Taking the heat off transactions: Dynamic selection of pessimistic concurrency control. 23rd IEEE International Symposium on Parallel {&} Distributed Processing (IPDPS 2009) 1–10 (2009).
Sonmez, N., Harris, T., Cristal, A., Unsal, O. & Valero, M. Taking the heat off transactions: Dynamic selection of pessimistic concurrency control. Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing 1–10 (2009).doi:10.1109/IPDPS.2009.5161032
Sönmez, N., Arcas, O., Pflucker, O., Cristal, A., Unsal, O., Hur, I., Singh, S. & Valero, M. TMbox: A Flexible and Reconfigurable 16-core Hybrid Transactional Memory System. The 19th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2011) 1–8 (2011).
Sonmez, N., Arcas, O., Pflucker, O., Unsal, O., Cristal, A., Hur, I., Singh, S. & Valero, M. {TMbox}: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System. Proc. FCCM '11 146–153 (2011).
Sonmez, N., Arcas, O., Pflucker, O., Unsal, O., Cristal, A., Hur, I., Singh, S. & Valero, M. TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System. Proc. FCCM '11 146–153 (2011).
Cristal, A., Santana, O.J., Valero, M. & Martínez, J.F. Toward Kilo-instruction Processors. ACM Transactions on Architecture and Code Optimization 1, 368–396 (2004).
Vallejo, E., Sanyal, S., Harris, T., Vallejo, F., Beivide, R., Unsal, O., Cristal, A. & Valero, M. Towards Fair Scalable Locking. Workshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods (EPHAM 2008) (2008).at <http://capinfo.e.ac.upc.edu/PDFs/dir22/file003705.pdf>
García, A., Medina, P., Fernández, E., Santana, O.J., Cristal, A. & Valero, M. Towards the Loop Processor Architecture. XVI Jornadas de Paralelismo (2005).
Smiljkovic, V., Stipić, S., Unsal, O., Cristal, A. & Valero, M. Transaction Coalescing - Lowering Transactional Overheads by Merging Transactions. Sixth Workshop on Programmability Issues for Heterogeneous Multicores (MULTIPROG-2013) (2013).
Kestor, G., Unsal, O., Cristal, A. & Valero, M. Transactional Look-based Parallel Program. Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008 71–75 (2008).
Harris, T., Cristal, A., Unsal, O., Ayguadé, E., Galiardi, F., Smith, B. & Valero, M. Transactional Memory: An Overview. IEEE Micro 27, 8–29 (2007).
Milovanovic, M., Ferrer, R., Unsal, O., Cristal, A., Martorell, X., Ayguadé, E., Labarta, J. & Valero, M. Transactional Memory and OpenMP. International Workshop on OpenMP (IWOMP-2007) 37–53 (2007).at <http://capinfo.e.ac.upc.edu/PDFs/dir05/file003195.pdf>
Negi, A., Armejach, A., Cristal, A., Unsal, O. & Stenström, P. Transactional prefetching: narrowing the window of contention in hardware transactional memory. Parallel Architectures and Compilation Techniques (PACT) 181-190 (2012).
Miletić, N., Smiljkovic, V., Perfumo, C., Harris, T., Cristal, A., Hur, I., Unsal, O. & Valero, M. Transactification of a real-world system library. 5th ACM SIGPLAN Workshop on Transactional Computing - TRANSACT 2010 (2010).
Hayes, T., Palomar, O., Unsal, O., Cristal, A. & Valero, M. True Vector Extensions for Decision Support DBMS Acceleration. (2011).
Kulkarni, C., Unsal, O., Cristal, A., Ayguadé, E. & Valero, M. Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions. ACM SIGPLAN Notices 44, 307–308 (2009).
Kulkarni, C., Unsal, O., Cristal, A., Ayguadé, E. & Valero, M. Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions. 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2009) 307–308 (2009).
Pericas, M., González, R., Cazorla, F., Cristal, A., Veidenbaum, A., Jiménez, D.A. & Valero, M. A two-level Load/Store Queue based on Execution Locality. (2008).
Pericàs, M., Cristal, A., Cazorla, F., González, R., Veidenbaum, A., Jiménez, D.A. & Valero, M. A Two-Level Load/Store Queue Based on Execution Locality. The 35th International Symposium on Computer Architecture (ISCA 2008) 25–36 (2008).at <http://capinfo.e.ac.upc.edu/PDFs/dir05/file003514.pdf>

Pages