Publications

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N. Sönmez, Arcas, O., Pflucker, O., Cristal, A., Unsal, O., Hur, I., Singh, S., and Valero, M., TMbox: A Flexible and Reconfigurable 16-core Hybrid Transactional Memory System, The 19th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2011). Salt Lake City, United States, pp. 1–8, 2011.
N. Sonmez, Arcas, O., Pflucker, O., Unsal, O., Cristal, A., Hur, I., Singh, S., and Valero, M., {TMbox}: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System, Proc. FCCM '11. pp. 146–153, 2011.
N. Sonmez, Arcas, O., Pflucker, O., Unsal, O., Cristal, A., Hur, I., Singh, S., and Valero, M., TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System, Proc. FCCM '11. pp. 146–153, 2011.
V. Smiljkovic, Nowack, M., Miletic, N., Harris, T., Unsal, O., Cristal, A., and Valero, M., TM-dietlibc: A TM-aware Real-world System Library, The 27th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2013). IEEE, Boston, United States, 2013.
A. Cristal, Santana, O. J., Valero, M., and Martínez, J. F., Toward Kilo-instruction Processors, ACM Transactions on Architecture and Code Optimization, vol. 1, pp. 368–396, 2004.
E. Vallejo, Sanyal, S., Harris, T., Vallejo, F., Beivide, R., Unsal, O., Cristal, A., and Valero, M., Towards Fair Scalable Locking, in Workshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods (EPHAM 2008), Boston, MA, United States, 2008.
A. García, Medina, P., Fernández, E., Santana, O. J., Cristal, A., and Valero, M., Towards the Loop Processor Architecture, in XVI Jornadas de Paralelismo, Granada, Spain, 2005.
V. Smiljkovic, Stipić, S., Unsal, O., Cristal, A., and Valero, M., Transaction Coalescing - Lowering Transactional Overheads by Merging Transactions, Sixth Workshop on Programmability Issues for Heterogeneous Multicores (MULTIPROG-2013). Berlin, Germany, 2013.
G. Kestor, Unsal, O., Cristal, A., and Valero, M., Transactional Look-based Parallel Program, in Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008, L'Aquila, Italy, 2008, pp. 71–75.
T. Harris, Cristal, A., Unsal, O., Ayguadé, E., Galiardi, F., Smith, B., and Valero, M., Transactional Memory: An Overview, IEEE Micro, vol. 27, pp. 8–29, 2007.
M. Milovanovic, Ferrer, R., Unsal, O., Cristal, A., Martorell, X., Ayguadé, E., Labarta, J., and Valero, M., Transactional Memory and OpenMP, in International Workshop on OpenMP (IWOMP-2007), Beijing, China, 2007, pp. 37–53.
A. Negi, Armejach, A., Cristal, A., Unsal, O., and Stenström, P., Transactional prefetching: narrowing the window of contention in hardware transactional memory, Parallel Architectures and Compilation Techniques (PACT). pp. 181-190, 2012.
N. Miletić, Smiljkovic, V., Perfumo, C., Harris, T., Cristal, A., Hur, I., Unsal, O., and Valero, M., Transactification of a real-world system library, 5th ACM SIGPLAN Workshop on Transactional Computing - TRANSACT 2010. Paris, France, 2010.
T. Hayes, Palomar, O., Unsal, O., Cristal, A., and Valero, M., True Vector Extensions for Decision Support DBMS Acceleration. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, 2011.
C. Kulkarni, Unsal, O., Cristal, A., Ayguadé, E., and Valero, M., Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions, in 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2009), Raleigh, North Carolina, United States, 2009, pp. 307–308.
C. Kulkarni, Unsal, O., Cristal, A., Ayguadé, E., and Valero, M., Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions, ACM SIGPLAN Notices, vol. 44, pp. 307–308, 2009.
M. Pericas, González, R., Cazorla, F., Cristal, A., Veidenbaum, A., Jiménez, D. A., and Valero, M., A two-level Load/Store Queue based on Execution Locality. In International Symposium on Computer Architecture. Beijing, China, 2008.
M. Pericàs, Cristal, A., Cazorla, F., González, R., Veidenbaum, A., Jiménez, D. A., and Valero, M., A Two-Level Load/Store Queue Based on Execution Locality, in The 35th International Symposium on Computer Architecture (ISCA 2008), Beijing, China, 2008, pp. 25–36.
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N. Sönmez, Cristal, A., Unsal, O., Harris, T., and Valero, M., Why you should profile Transactional Memory Applications on an Atomic Block basis: A Haskell Case Study. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, 2008.
F. Zyulkyarov, Cristal, A., Cvijic, S., Ayguadé, E., Valero, M., Unsal, O., and Harris, T., WormBench: a configurable workload for evaluating transactional memory systems, in 9th workshop on MEmory performance: DEaling with Applications, systems and architecture (MEDEA 2008), Toronto, Canada, 2008, pp. 61–68.

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