Publications

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E
Sánchez, F., Ramirez, A. & Valero, M. Exploiting Different Levels of Parallelism in the Biological Sequence Comparison Problem. 4CCC. 4th Colombian Computing Conference (2009).
Moreto, M., Cazorla, F., Ramirez, A. & Valero, M. Explaining Dynamic Cache Partitioning Speed Ups. IEEE Computer Architecture Letters 6, 1-12 (2007).
Cazorla, F., Medina, P., Fernández, E., Ramirez, A. & Valero, M. Estudio y evaluación de mecanismos de control de la Especulación. In XIII Jornadas de Paralelismo, Lleida (Spain) (2002).
Santana, O.J., Ramirez, A. & Valero, M. Enlarging Instruction Streams. IEEE Transactions on Computers 56, 1342-1357 (2007).
Göddeke, D., Komatitsch, D., Geveler, M., Ribbrock, D., Rajovic, N., Puzovic, N. & Ramirez, A. Energy efficiency vs. performance of the numerical solution of PDEs: An application study on a low-power ARM-based cluster. Journal of Computational Physics 237, 132--150 (2012).
Cazorla, F., Knijnenburg, P., Sakellariou, R., Fernandez, E., Ramirez, A. & Valero, M. Enabling SMT for Real-Time Embedded Systems. European Signal Processing Conference (EUSIPCO) (2004).
Falcón, A., Ramirez, A. & Valero, M. Effective Instruction Prefetching via Fetch Prestaging. IPDPS05. IEEE-ACM 19th International Parallel and Distributed Processing Symposium (2005).
Ramirez, A., Larriba-Pey, J.L. & Valero, M. The Effect of Code Reordering on Branch Prediction. International Conference on Parallel Architectures and Compilation Techniques (PACT 2000) 189-198 (2000).
D
Cazorla, F., Ramirez, A., Valero, M. & Fernández, E. Dynamically Controlled Resource Allocation in SMT Processors. 37th Annual International Symposium on Microarchitecture (MICRO-37) 171-182 (2004).
Cazorla, F., Fernández, E., Ramirez, A. & Valero, M. Dynamically Controlled Resource Allocation in SMT. XVI Jornadas de Paralelismo. Granada (2005).
Moreto, M., Cazorla, F., Ramirez, A. & Valero, M. Dynamic Cache Partitioning Based on the MLP on Cache Misses. Transactions on HiPEAC 3, 1-21 (2008).
Vujic, N., Cabarcas, F., González, M., Ramirez, A., Martorell, X. & Ayguadé, E. DMA++: On the Fly Data Realignment for On-Chip Memories. Computers, IEEE Transactions on 61, 237 -250 (2012).
Vujic, N., González, M., Ayguadé, E., Martorell, X., Ramirez, A. & Cabarcas, F. DMA++: On the Fly Data Realignment for On-Chip Memories. 16th IEEE International Symposium on High-Performance Computer Architecture (2010).
González, I., Galluzzi, M., Veidenbaum, A., Ramirez, A., Cristal, A. & Valero, M. A distributed processor state management architecture for large-window processors. 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41) 11–22 (2008).at <http://capinfo.e.ac.upc.edu/PDFs/dir14/file003697.pdf>
Villavieja, C., Karakostas, V., Vilanova, L., Etsion, Y., Ramirez, A., Mendelson, A., Navarro, N., Cristal, A. & Unsal, O. DiDi: Mitigating The Performance Impact of TLB Shootdowns Using A Shared TLB Directory. Parallel Architectures and Compilation Techniques (PACT) (2011).
Santana, O.J., Falcón, A., Ramirez, A. & Valero, M. DIA: A Complexity-Effective Decoding Architecture. IEEE Transactions on Computers 58, 448-462 (2009).
Acosta, C., Galluzzi, M., Vajapeyam, S., Ramirez, A. & Valero, M. Dealing with Billions of Transistors. XIV Jornadas de Paralelismo 547-552 (2003).
Cazorla, F., Fernández, E., Ramirez, A. & Valero, M. DCache Warn: An I-Fetch Policy To Increase SMT Efficiency. 18th International Parallel and Distributed Processing Symposium (IPDPS-2004) (2004).
C
Etsion, Y., Ramirez, A., Badia, R.M. & Labarta, J. Cores as Functional Units: A Task-Based, Out-of-Order, Dataflow Pipeline. Advanced Computer Architecture and Compilation for Embedded Systems (ACACES) (2009).
Acosta, C., Cazorla, F., Ramirez, A. & Valero, M. Core to Memory Interconnection Implications for Forthcoming On-Chip Multiprocessors. 1st Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI 2007) (2007).
Santana, O.J., Falcón, A., Fernández, E., Medina, P., Ramirez, A. & Valero, M. A Comprehensive Analysis of Indirect Branch Prediction. 4th International Symposium on High Performance Computing (ISHPC-4) 133-141 (2002).
Acosta, C., Falcón, A., Ramirez, A. & Valero, M. Complexity-Effectiveness in Multithreading Architectures. In 2005 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-2005) 79-82 (2005).
Acosta, C., Falcón, A., Ramirez, A. & Valero, M. A Complexity-Effective Simultaneous Multithreading Architecture. 34th International Conference on Parallel Processing (ICPP 2005) (2005).
Santana, O.J., Falcón, A., Ramirez, A. & Valero, M. A Complexity-Effective Decoding Architecture Based on Instruction Streams. Workshop on Complexity-Effective Design (WCED) (2004).
Vega, A., Rico, A., Cabarcas, F., Ramirez, A. & Valero, M. Comparing last-level cache designs for CMP architectures. IFMT '10: International Forum on Next-Generation Multicore/Manycore Technologies (2010).
Vandierendonck, H., Ramirez, A., Bosschere, K.D. & Valero, M. A comparative study of redundancy in trace caches. Intl. Euro-Par Conference 512-516 (2002).
Ramirez, A., Barroso, L.A., Gharachorloo, K., Cohn, R., Larriba-Pey, J.L., Lowney, G. & Valero, M. Code Layout Optimizations for Transaction Processing Workloads. 28th Annual International Symposium on Computer Architecture (ISCA-28) 155-164 (2001).
Bellens, P., Pérez, J.M., Cabarcas, F., Ramirez, A., Badia, R.M. & Labarta, J. CellSs: Scheduling Techniques to Better Exploit Memory Hierarchy. (2009).
Cabarcas, F., Rico, A., Ródenas, D., Martorell, X., Ramirez, A. & Ayguadé, E. CellSim: A Validated Modular Heterogeneous Multiprocessor Simulator. XVIII Jornadas de Paralelismo de Zaragoza 181-188 (2007).
Cabarcas, F., Rico, A., Ródenas, D., Martorell, X., Ramirez, A. & Ayguadé, E. CellSim: A Cell Processor Simulation Infrastructure. 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07) 279-282 (2007).
Acosta, C., Vajapeyam, S., Ramirez, A. & Valero, M. CDE: A Compiler-driven, Dependence-Centric, Eager-executing Architecture for the Billion Transistors Era. Workshop on Complexity-Effective Design (WCED 2003) (2003).
Pavlovic, M., Etsion, Y. & Ramirez, A. Can Manycores Support the Memory Requirements of Scientific Applications?. Workshop on Applications for Multi and Many Core Processors (A4MMC) (2010).
B
Carpenter, P., Ramirez, A. & Ayguadé, E. Buffer sizing for self-timed stream programs on heterogeneous distributed memory multiprocessors. International conference on High-Performance Embedded Architectures and Compilers (HiPEAC) 2010 96-110 (2010).
Santana, O.J., Falcón, A., Ramirez, A. & Valero, M. Branch Predictor Guided Instruction Decoding. IEEE Intl. Conference on Parallel Architectures and Compiler Techniques (PACT-2006) (2006).
Ramirez, A., Larriba-Pey, J.L. & Valero, M. Branch Prediction Using Profile Data. 7th International Euro-Par Conference (Euro-Par'2001) 386-393 (2001).
Knijnenburg, P., Ramirez, A., Latorre, F., Larriba-Pey, J.L. & Valero, M. Branch Classification to Control Instruction Fetch in Simultaneous Multithreaded Architectures. International Workshop on Innovative Architecture (IWIA 2002) 67-76 (2002).
Knijnenburg, P., Ramirez, A., Larriba-Pey, J.L. & Valero, M. Branch classification for SMT fetch gating. 6th Workshop on Multithreaded Execution, Architecture and Compilation (MTEAC6) (2002).
Falcón, A., Stark, J., Ramirez, A., Lai, K. & Valero, M. Better branch prediction through prophet/critic hybrids. IEEE Micro 25, 80-89 (2005).
A
Rico, A., Ramirez, A. & Valero, M. Available task-level parallelism on the Cell BE. Scientific Programming 17, 59-76 (2009).
Cazorla, F., Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A. & Valero, M. Architectural Support for Real-Time Task Scheduling in SMT Processors. International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES-2005) (2005).
Cazorla, F., Fernández, E., Ramirez, A. & Valero, M. Approaching a Smart Sharing of Resources in SMT Processors. Workshop on Complexity-Effective Design (WCED) (2004).
Azevedo, A., Meenderinck, C., Juurlink, B., Álvarez, M. & Ramirez, A. Analysis of Video Filtering on the Cell Processor. 2008 IEEE International Symposium on Circuits and Systems (ISCAS'08) 488-491 (2008).
Santana, O.J., Galluzzi, M., Ramirez, A. & Valero, M. An Analysis of Dynamic Instruction Streams. XIV Jornadas de Paralelismo 527-532 (2003).
Falcón, A., Santana, O.J., Medina, P., Fernández, E., Ramirez, A. & Valero, M. An Analysis of Dynamic History Length Fitting. XII Jornadas de Paralelismo, Valencia (Spain) (2001).
García, A., Fernández, E., Medina, P., Ramirez, A. & Valero, M. Analisis y caracterización de los bucles. XIII Jornadas de Paralelismo (2002).
Carpenter, P., Ramirez, A. & Ayguadé, E. The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors. IX International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS Workshop IX) 12-23 (2009).
Carpenter, P., Ramirez, A. & Ayguadé, E. The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors. Transactions on HiPEAC 5, (2011).
3
Vega, A., Ramirez, A. & Valero, M. 3D Die-Stacking Architectures: State of the Art. Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008 203-207 (2008).

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