Publications

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García, A. et al. Towards the Loop Processor Architecture. XVI Jornadas de Paralelismo (Thomson, 2005).
Cristal, A., Santana, O. J., Valero, M. & Martínez, J. F. Toward Kilo-instruction Processors. ACM Transactions on Architecture and Code Optimization 1, 368–396 (2004).
Falcón, A., Santana, O. J., Ramirez, A. & Valero, M. Tolerating branch predictor latency on SMT. 5th International Symposium on High Performance Computing (ISHPC-V) 86-98 (2003).
R
García, A. et al. Reducing the Activity of Instruction Renaming in Loop Structures. II Congreso Español de Informática (CEDI 2007) (2007).
Santana, O. J., Ramirez, A. & Valero, M. Reducing Fetch Architecture Complexity Using Procedure Inlining. 8th Workshop on Interaction between Compilers and Computer Architectures (INTERACT) (2004).
L
Santana, O. J., Ramirez, A., Larriba-Pey, J. L. & Valero, M. A Low-Complexity Fetch Architecture for High-Performance Superscalar Processors. ACM Transactions on Architecture and Code Optimization 1, 220-245 (2004).
Valero, M., Santana, O. J., Ramirez, A. & Larriba-Pey, J. L. A Low Complexity Fetch Architecture for High Performance Superscalar Processors. ACM Transactions on Architecture and Compiler Optimizations (TACO) 1, 220-245 (2004).
Vera, J. et al. Looking for novel ways to obtain fair measurements in multithreaded architectures. (2006).
Santana, O. J., Ramirez, A. & Valero, M. Latency Tolerant Branch Predictors. 2003 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'03) 30-39 (2003).
Falcón, A., Santana, O. J., Ramirez, A. & Valero, M. A latency conscious SMT branch predictor architecture. International Journal of High Performance Computing and Networking (IJHPCN) 2, 11-21 (2004).
C
Cristal, A., Santana, O. J. & Valero, M. A Comprehensive Description of Kilo-Instruction Processors. 5o Congreso Nacional de Computación 144–154 (Instituto Politécnico Nacional - Centro de Investigación en Computación, 2004).
Santana, O. J. et al. A Comprehensive Analysis of Indirect Branch Prediction. 4th International Symposium on High Performance Computing (ISHPC-4) 133-141 (2002).
Santana, O. J., Falcón, A., Ramirez, A. & Valero, M. A Complexity-Effective Decoding Architecture Based on Instruction Streams. Workshop on Complexity-Effective Design (WCED) (2004).
B
Santana, O. J., Falcón, A., Ramirez, A. & Valero, M. Branch Predictor Guided Instruction Decoding. IEEE Intl. Conference on Parallel Architectures and Compiler Techniques (PACT-2006) (2006).