Publications

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García, A., Medina, P., Fernández, E., Santana, O.J., Cristal, A. & Valero, M. Towards the Loop Processor Architecture. XVI Jornadas de Paralelismo (2005).
Cristal, A., Santana, O.J., Valero, M. & Martínez, J.F. Toward Kilo-instruction Processors. ACM Transactions on Architecture and Code Optimization 1, 368–396 (2004).
Falcón, A., Santana, O.J., Ramirez, A. & Valero, M. Tolerating branch predictor latency on SMT. 5th International Symposium on High Performance Computing (ISHPC-V) 86-98 (2003).
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Falcón, A., Santana, O.J., Medina, P., Fernández, E., Ramirez, A. & Valero, M. Studying New Ways for Improving Adaptive History Length Branch Predictors. 4th International Symposium on High Performance Computing (ISHPC-4) 271-279 (2002).
Santana, O.J., Falcón, A., Ramirez, A. & Valero, M. Stream Predictor Guided Instruction Decoding. XV Jornadas de Paralelismo 184-189 (2004).
Ramírez, T., Pajuelo, M., Santana, O.J. & Valero, M. A Simple Speculative Load Control Mechanism for Energy Saving. (2006).
Falcón, A., Santana, O.J., Ramirez, A. & Valero, M. Selecting Where to Simulate SPEC2000 Using Streams Analysis. XV Jornadas de Paralelismo 208--213 (2004).
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García, A., Santana, O.J., Fernández, E., Medina, P., Cristal, A. & Valero, M. Reducing the Activity of Instruction Renaming in Loop Structures. II Congreso Español de Informática (CEDI 2007) (2007).
Santana, O.J., Ramirez, A. & Valero, M. Reducing Fetch Architecture Complexity Using Procedure Inlining. 8th Workshop on Interaction between Compilers and Computer Architectures (INTERACT) (2004).
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Cazorla, F., Pajuelo, A., Santana, O.J., Fernandez, E. & Valero, M. On the Problem of Evaluating the Performance of Multiprogrammed Workloads. . IEEE Transactions on Computers 59, (2010).
Santana, O.J., Ramirez, A. & Valero, M. Predicting two Streams per Cycle. XVI Jornadas de Paralelismo 3-10 (2005).
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Vera, J., Cazorla, F., Pajuelo, A., Santana, O.J., Fernández, E. & Valero, M. A Novel Evaluation Methodology to Obtain Fair Measurements in Multithreaded Architectures. (2006).
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Santana, O.J., Ramirez, A. & Valero, M. Multiple Stream Prediction. ISHPC. International Symposium on High Performance Computers (2005).
Vera, J., Cazorla, F., Pajuelo, A., Santana, O.J., Fernández, E. & Valero, M. Measuring the Performance of Multithreaded Processors. (2007).
Cristal, A., Santana, O.J. & Valero, M. Maintaining Thousands of In-Flight Instructions. 10th International Euro-Par 2004 Conference 9–20 (2004).
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Santana, O.J., Ramirez, A., Larriba-Pey, J.L. & Valero, M. A Low-Complexity Fetch Architecture for High-Performance Superscalar Processors. ACM Transactions on Architecture and Code Optimization 1, 220-245 (2004).
Valero, M., Santana, O.J., Ramirez, A. & Larriba-Pey, J.L. A Low Complexity Fetch Architecture for High Performance Superscalar Processors. ACM Transactions on Architecture and Compiler Optimizations (TACO) 1, 220-245 (2004).
Vera, J., Cazorla, F., Pajuelo, A., Santana, O.J., Fernández, E. & Valero, M. Looking for novel ways to obtain fair measurements in multithreaded architectures. (2006).
Santana, O.J., Ramirez, A. & Valero, M. Latency Tolerant Branch Predictors. 2003 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'03) 30-39 (2003).
Falcón, A., Santana, O.J., Ramirez, A. & Valero, M. A latency conscious SMT branch predictor architecture. International Journal of High Performance Computing and Networking (IJHPCN) 2, 11-21 (2004).
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Ramírez, T., Pajuelo, M., Santana, O.J. & Valero, M. Kilo-instruction Processors, Runahead and Prefetching. (2006).
Ramírez, T., Cristal, A., Santana, O.J., Pajuelo, A. & Valero, M. Kilo-Instruction Processors, RunAhead and Prefetch. ACM International Conference on Computing Frontiers (CF 2006) (2006).at <http://capinfo.e.ac.upc.edu/PDFs/dir05/file003137.pdf>
Cristal, A., Santana, O.J., Cazorla, F., Galluzzi, M., Ramírez, T., Pericàs, M. & Valero, M. Kilo-instruction Processors: Overcoming the Memory Wall. IEEE Micro 25, 48–57 (2005).
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Galluzzi, M., Puente, V., Santana, O.J., Acosta, C., Cristal, A., Beivide, R., Monasterio, J.A.G. & Valero, M. Introducing Kilo-instruction Multiprocessors. XV Jornadas de Paralelismo (2004).at <http://capinfo.e.ac.upc.edu/PDFs/dir19/file002977.pdf>
Santana, O.J., Falcón, A., Fernández, E., Medina, P., Ramirez, A. & Valero, M. An In-Depth Evaluation of the Multi-Stage Cascaded Predictor. XII Jornadas de Paralelismo, Valencia (Spain) (2001).
González, I., Santana, O.J., Pajuelo, A. & Valero, M. Implementando recuperaciones precisas en procesadores con consolidación fuera de orden. (2006).
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González, I., Santana, O.J., Pajuelo, A. & Valero, M. A First Glance at the Implementation of Precise Recoveries in Out-of-order Commit Processors. (2006).
Ramirez, A., Santana, O.J., Larriba-Pey, J.L. & Valero, M. Fetching Instruction Streams. 35th Annual International Symposium on Microarchitecture (MICRO-35) 371-382 (2002).
Vera, J., Cazorla, F., Pajuelo, A., Santana, O.J., Fernández, E. & Valero, M. FAME: FAirly MEasuring Multithreaded Architectures. (2007).at <http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4336221>
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Santana, O.J., Ramirez, A. & Valero, M. Enlarging Instruction Streams. IEEE Transactions on Computers 56, 1342-1357 (2007).
Ramírez, T., Cristal, A., Pajuelo, A., Santana, O.J. & Valero, M. Eficacia vs. Eficiencia: Una decisión de diseño en Runahead. XVI Jornadas de Paralelismo (2005).at <http://capinfo.e.ac.upc.edu/PDFs/dir01/file003075.pdf>
Ramírez, T., Santana, O.J., Pajuelo, A. & Valero, M. Efficient runahead threads. (2011).
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Santana, O.J., Falcón, A., Ramirez, A. & Valero, M. DIA: A Complexity-Effective Decoding Architecture. IEEE Transactions on Computers 58, 448-462 (2009).
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Cristal, A., Santana, O.J. & Valero, M. A Comprehensive Description of Kilo-Instruction Processors. 5o Congreso Nacional de Computación 144–154 (2004).
Santana, O.J., Falcón, A., Fernández, E., Medina, P., Ramirez, A. & Valero, M. A Comprehensive Analysis of Indirect Branch Prediction. 4th International Symposium on High Performance Computing (ISHPC-4) 133-141 (2002).
Santana, O.J., Falcón, A., Ramirez, A. & Valero, M. A Complexity-Effective Decoding Architecture Based on Instruction Streams. Workshop on Complexity-Effective Design (WCED) (2004).
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Santana, O.J., Falcón, A., Ramirez, A. & Valero, M. Branch Predictor Guided Instruction Decoding. IEEE Intl. Conference on Parallel Architectures and Compiler Techniques (PACT-2006) (2006).
A
Santana, O.J., Galluzzi, M., Ramirez, A. & Valero, M. An Analysis of Dynamic Instruction Streams. XIV Jornadas de Paralelismo 527-532 (2003).
Falcón, A., Santana, O.J., Medina, P., Fernández, E., Ramirez, A. & Valero, M. An Analysis of Dynamic History Length Fitting. XII Jornadas de Paralelismo, Valencia (Spain) (2001).