Publications

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A. García, Medina, P., Fernández, E., Santana, O. J., Cristal, A., and Valero, M., Towards the Loop Processor Architecture, in XVI Jornadas de Paralelismo, Granada, Spain, 2005.
A. Cristal, Santana, O. J., Valero, M., and Martínez, J. F., Toward Kilo-instruction Processors, ACM Transactions on Architecture and Code Optimization, vol. 1, pp. 368–396, 2004.
A. Falcón, Santana, O. J., Ramirez, A., and Valero, M., Tolerating branch predictor latency on SMT, 5th International Symposium on High Performance Computing (ISHPC-V). Tokio (Japan), pp. 86-98, 2003.
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J. Vera, Cazorla, F., Pajuelo, A., Santana, O. J., Fernández, E., and Valero, M., A Novel Evaluation Methodology to Obtain Fair Measurements in Multithreaded Architectures. In Workshop on Modeling, Benchmarking and Simulation (MoBS)2006. Held in conjunction with ISCA, Boston, USA, 2006.
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O. J. Santana, Ramirez, A., and Valero, M., Multiple Stream Prediction, ISHPC. International Symposium on High Performance Computers. Springer-Verlag, 2005.
J. Vera, Cazorla, F., Pajuelo, A., Santana, O. J., Fernández, E., and Valero, M., Measuring the Performance of Multithreaded Processors. In SPEC Benchmark Workshop (in conjunction with the Annual Meeting of the Standard Performance Evaluation Corporation (SPEC)), Austin, USA, 2007.
A. Cristal, Santana, O. J., and Valero, M., Maintaining Thousands of In-Flight Instructions, in 10th International Euro-Par 2004 Conference, Pisa, Italy, 2004, pp. 9–20.
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O. J. Santana, Ramirez, A., Larriba-Pey, J. L., and Valero, M., A Low-Complexity Fetch Architecture for High-Performance Superscalar Processors, ACM Transactions on Architecture and Code Optimization, vol. 1, no. 2. pp. 220-245, 2004.
M. Valero, Santana, O. J., Ramirez, A., and Larriba-Pey, J. L., A Low Complexity Fetch Architecture for High Performance Superscalar Processors, ACM Transactions on Architecture and Compiler Optimizations (TACO), vol. 1, no. 2. pp. 220-245, 2004.
J. Vera, Cazorla, F., Pajuelo, A., Santana, O. J., Fernández, E., and Valero, M., Looking for novel ways to obtain fair measurements in multithreaded architectures. XVII Jornadas de Paralelismo, 2006.
O. J. Santana, Ramirez, A., and Valero, M., Latency Tolerant Branch Predictors, 2003 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'03). Kauai, Hawaii (United States), pp. 30-39, 2003.
A. Falcón, Santana, O. J., Ramirez, A., and Valero, M., A latency conscious SMT branch predictor architecture, International Journal of High Performance Computing and Networking (IJHPCN), vol. 2, no. 1. pp. 11-21, 2004.
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O. J. Santana, Ramirez, A., and Valero, M., Enlarging Instruction Streams, IEEE Transactions on Computers, vol. 56, no. 10. pp. 1342-1357, 2007.
T. Ramírez, Cristal, A., Pajuelo, A., Santana, O. J., and Valero, M., Eficacia vs. Eficiencia: Una decisión de diseño en Runahead, in XVI Jornadas de Paralelismo, Granada, Spain, 2005.
T. Ramírez, Santana, O. J., Pajuelo, A., and Valero, M., Efficient runahead threads. PACT 2010. International Conference on Parallel Architectures and Compiler Techniques, 2011.
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A. Cristal, Santana, O. J., and Valero, M., A Comprehensive Description of Kilo-Instruction Processors, in 5o Congreso Nacional de Computación, Mexico City, Mexico, 2004, pp. 144–154.
O. J. Santana, Falcón, A., Fernández, E., Medina, P., Ramirez, A., and Valero, M., A Comprehensive Analysis of Indirect Branch Prediction, 4th International Symposium on High Performance Computing (ISHPC-4). Springer-Verlag, Kansai Science City (Japan), pp. 133-141, 2002.
O. J. Santana, Falcón, A., Ramirez, A., and Valero, M., A Complexity-Effective Decoding Architecture Based on Instruction Streams, Workshop on Complexity-Effective Design (WCED). 2004.
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O. J. Santana, Falcón, A., Ramirez, A., and Valero, M., Branch Predictor Guided Instruction Decoding, IEEE Intl. Conference on Parallel Architectures and Compiler Techniques (PACT-2006). 2006.