Publications

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Verdú, J., García, J., Nemirovsky, M. & Valero, M. Analysis of Traffic Traces for Statefull Applications. (2004).
Verdú, J., García, J., Nemirovsky, M. & Valero, M. Analysis of Traffic Traces for Stateful Applications. (2004).
Kedzierski, K., Cazorla, F. & Valero, M. Analysis of Simultaneous Multithreading Implementations in Current High-Performance Processors. (2006).
Kedzierski, K., Cazorla, F. & Valero, M. Analysis of multithreading capabilities of current high-performance processors. (2006).
Santana, O. J., Galluzzi, M., Ramirez, A. & Valero, M. An Analysis of Dynamic Instruction Streams. XIV Jornadas de Paralelismo 527-532 (2003).
Falcón, A. et al. An Analysis of Dynamic History Length Fitting. XII Jornadas de Paralelismo, Valencia (Spain) (2001).
March, M., García, J., Cerdá, L. & Valero, M. Analysis of a high performance DRAM/SRAM memory scheme for fast packet buffers. (2004).
García, A., Fernández, E., Medina, P., Ramirez, A. & Valero, M. Analisis y caracterización de los bucles. XIII Jornadas de Paralelismo (2002).
Pajuelo, A., González, A. & Valero, M. Aggressive Speculative Execution for Hidding Memory Latency. (2004).
Kedzierski, K., Moreto, M., Cazorla, F. & Valero, M. Adapting Cache Partitioning Algorithms to Real pseudo-LRU Replacement Policies. (2010).
Maric, B., Abella, J. & Valero, M. ADAM: An Efficient Data Management Mechanism for Hybrid High and Ultra-Low Voltage Operation Caches. ACM/IEEE Great Lakes Symposium on VLSI 245–250 (2012). at <http://capinfo.e.ac.upc.edu/PDFs/dir05/file004123.pdf>
3
Vega, A., Ramirez, A. & Valero, M. 3D Die-Stacking Architectures: State of the Art. Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008 203-207 (2008).

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