Publications

Export 342 results:
Sort by: Author [ Title (Desc)] Type Year
Filters: Author is Mateo Valero  [Clear All Filters]
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 
C
Acosta, C., Vajapeyam, S., Ramirez, A. & Valero, M. CDE: A Compiler-driven, Dependence-Centric, Eager-executing Architecture for the Billion Transistors Era. Workshop on Complexity-Effective Design (WCED 2003) (2003).
Cristal, A., Martínez, J.F., Llosa, J. & Valero, M. A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors. ACM SIGARCH Computer Architecture News 32, 3–10 (2004).
Cristal, A., Martínez, J.F., Llosa, J. & Valero, M. A Case for Resource-conscious Out-of-order Processors. (2003).
Cristal, A., Martínez, J.F., Llosa, J. & Valero, M. A Case for Resource-conscious Out-of-order Processors. Computer Architecture Letters 2, (2003).
Cristal, A., Martínez, J.F., Llosa, J. & Valero, M. A Case for Resource Conscious Out-of-Order Processor. MEDEA Workshop MEmory performance: DEaling with Applications , systems and architecture (MEDEA 2003) (2003).
Jimenez, V., Cazorla, F., Gioiosa, R., Kursun, E., Isci, C., Buyuktosunoglu, A., Bose, P. & Valero, M. A Case for Energy-Aware Accounting and Billing in Large-Scale Computing Facilities Cost Metrics and Design Implications. IEEE Micro (2011).
Jiménez, V.J., Cazorla, F., Gioiosa, R., Kursun, E., Isci, C., Buyuktosunoglu, A. & Valero, M. A Case for Energy Aware Accounting in Large Scale Computing Facilities: Cost Metrics and Implications for Processor Design. (2010).
B
Etinski, M., Corbalán, J., Labarta, J. & Valero, M. BSLD Threshold Driven Power Management Policy for HPC Centers. (2010).
Torres, J., Ayguadé, E., Carrera, D., Guitart, J., Beltran, V., Becerra, Y., Badia, R.M., Labarta, J. & Valero, M. BSC contributions in Energy-aware Resource Management for Large Scale Distributed Systems. 1st Year Workshop of the COST Action IC0804 on Energy Efficiency in Large Scale Distributed Systems 76-79 (2010).
Santana, O.J., Falcón, A., Ramirez, A. & Valero, M. Branch Predictor Guided Instruction Decoding. IEEE Intl. Conference on Parallel Architectures and Compiler Techniques (PACT-2006) (2006).
Ramirez, A., Larriba-Pey, J.L. & Valero, M. Branch Prediction Using Profile Data. 7th International Euro-Par Conference (Euro-Par'2001) 386-393 (2001).
Knijnenburg, P., Ramirez, A., Latorre, F., Larriba-Pey, J.L. & Valero, M. Branch Classification to Control Instruction Fetch in Simultaneous Multithreaded Architectures. International Workshop on Innovative Architecture (IWIA 2002) 67-76 (2002).
Knijnenburg, P., Ramirez, A., Larriba-Pey, J.L. & Valero, M. Branch classification for SMT fetch gating. 6th Workshop on Multithreaded Execution, Architecture and Compilation (MTEAC6) (2002).
Pericàs, M., Cristal, A., González, R., Cazorla, F., Jiménez, D.A. & Valero, M. Boosting ILP{&}TLP with the Flexible Multi-Core (FMC). 2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06) 125–128 (2006).
Falcón, A., Stark, J., Ramirez, A., Lai, K. & Valero, M. Better branch prediction through prophet/critic hybrids. IEEE Micro 25, 80-89 (2005).
Pericàs, M., González, R., Cristal, A., Veidenbaum, A. & Valero, M. Banked Front-End Register File. (2004).
Boneti, C., Cazorla, F., Gioiosa, R., Corbalán, J., Labarta, J. & Valero, M. Balancing HPC Applications Through Smart Allocation of Resources in MT Processors. (2008).at <http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4536293>
A
Rico, A., Ramirez, A. & Valero, M. Available task-level parallelism on the Cell BE. Scientific Programming 17, 59-76 (2009).
Zyulkyarov, F., Gajinov, V., Unsal, O., Cristal, A., Ayguadé, E., Harris, T. & Valero, M. Atomic Quake: Using Transactional Memory in an Interactive Multiplayer Game Server. 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2009) 25–34 (2009).
González, R., Cristal, A., Pericàs, M., Valero, M. & Veidenbaum, A. An asymetric Clustered Processor Based on Value Content. The 19th ACM International Conference on Supercomputing (ICS'05) 61–70 (2005).at <http://capinfo.e.ac.upc.edu/PDFs/dir24/file003040.pdf>
Araya-Polo, M., Cabezas, J., Hanzich, M., Pericas, M., Morancho, E., Gelado, I., Shafiq, M., Rubio, F., Cela, J.M., Ayguadé, E., Navarro, N. & Valero, M. Assessing Accelerator-based HPC Reverse Time Migration. Transactions on Parallel and Distributed Systems, Special Issue on Accelerators 22(1), 147-162 (2011).
González, R., Cristal, A., Ortega, D. & Valero, M. Arquitecturas Basadas en el Contenido. XIV Jornadas de Paralelismo 541–546 (2003).
González, R., Cristal, A., Pericàs, M., Veidenbaum, A. & Valero, M. Arquitectura Simétrica Clusterizada basada en el Contenido. XVI Jornadas de Paralelismo (2005).
Castillo, P.A., Mora, A.M., Merelo, J.J., Laredo, J.L., Moreto, M., Cazorla, F., Valero, M. & McKee, S.A. Architecture performance prediction using evolutionary artificial neural networks. (2008).
Markovic, N., González, R., Unsal, O., Valero, M. & Cristal, A. Architecture for Object-Oriented Programming Model. (2009).at <http://capinfo.e.ac.upc.edu/PDFs/dir11/file003491.pdf>
Cazorla, F., Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A. & Valero, M. Architectural Support for Real-Time Task Scheduling in SMT Processors. International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES-2005) (2005).
Vallejo, E., Beivide, R., Cristal, A., Harris, T., Vallejo, F., Unsal, O. & Valero, M. Architectural Support for Fair Reader-Writer Locking. International Symposium on Microarchitecture (2010).
Valero, M., Verdú, J., Nemirovsky, M. & García, J. Architectural Impact of Statefull Networking APPlications. (2005).
Cazorla, F., Fernández, E., Ramirez, A. & Valero, M. Approaching a Smart Sharing of Resources in SMT Processors. Workshop on Complexity-Effective Design (WCED) (2004).
Paolieri, M., Quiñones, E., Cazorla, F. & Valero, M. An Analyzable Memory Controller for Hard Real-Time CMPs. IEEE Embedded Systems Letters 1, (2009).
Verdú, J., García, J., Nemirovsky, M. & Valero, M. Analysis of Traffic Traces for Statefull Applications. (2004).
Verdú, J., García, J., Nemirovsky, M. & Valero, M. Analysis of Traffic Traces for Stateful Applications. (2004).
Kedzierski, K., Cazorla, F. & Valero, M. Analysis of Simultaneous Multithreading Implementations in Current High-Performance Processors. (2006).
Kedzierski, K., Cazorla, F. & Valero, M. Analysis of multithreading capabilities of current high-performance processors. (2006).
Santana, O.J., Galluzzi, M., Ramirez, A. & Valero, M. An Analysis of Dynamic Instruction Streams. XIV Jornadas de Paralelismo 527-532 (2003).
Falcón, A., Santana, O.J., Medina, P., Fernández, E., Ramirez, A. & Valero, M. An Analysis of Dynamic History Length Fitting. XII Jornadas de Paralelismo, Valencia (Spain) (2001).
March, M., García, J., Cerdá, L. & Valero, M. Analysis of a high performance DRAM/SRAM memory scheme for fast packet buffers. (2004).
García, A., Fernández, E., Medina, P., Ramirez, A. & Valero, M. Analisis y caracterización de los bucles. XIII Jornadas de Paralelismo (2002).
Pajuelo, A., González, A. & Valero, M. Aggressive Speculative Execution for Hidding Memory Latency. (2004).
Kedzierski, K., Moreto, M., Cazorla, F. & Valero, M. Adapting Cache Partitioning Algorithms to Real pseudo-LRU Replacement Policies. (2010).
Maric, B., Abella, J. & Valero, M. ADAM: An Efficient Data Management Mechanism for Hybrid High and Ultra-Low Voltage Operation Caches. ACM/IEEE Great Lakes Symposium on VLSI 245–250 (2012).at <http://capinfo.e.ac.upc.edu/PDFs/dir05/file004123.pdf>
3
Vega, A., Ramirez, A. & Valero, M. 3D Die-Stacking Architectures: State of the Art. Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008 203-207 (2008).

Pages