Publications

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A
E. Vallejo, Beivide, R., Cristal, A., Harris, T., Vallejo, F., Unsal, O., and Valero, M., Architectural Support for Fair Reader-Writer Locking, in International Symposium on Microarchitecture, Atlanta, United States, 2010.
M. Valero, Verdú, J., Nemirovsky, M., and García, J., Architectural Impact of Statefull Networking APPlications. ANCS-2005. IEEE and ACM Symposium on Architectures for Networking and Communications Systems, 2005.
F. Cazorla, Fernández, E., Ramirez, A., and Valero, M., Approaching a Smart Sharing of Resources in SMT Processors, Workshop on Complexity-Effective Design (WCED). 2004.
B. Maric, Abella, J., and Valero, M., APPLE: Adaptive Performance-Predictable Low-Energy Caches for Reliable Hybrid Voltage Operation, 50th Annual Design Automation Conference (DAC). ACM, Austin (Texas), United States, pp. 1–6, 2013.
B. Maric, Abella, J., and Valero, M., Analyzing the Efficiency of L1 Caches for Reliable Hybrid-Voltage Operation Using EDC Codes, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22. pp. 2211–2215, 2014.
B. Maric, Abella, J., and Valero, M., Analyzing the Efficiency of L1 Caches for Reliable Hybrid-Voltage Operation Using EDC Codes, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 22, no. 10. pp. 2211 - 2215, 2014.
M. Paolieri, Quiñones, E., Cazorla, F., and Valero, M., An Analyzable Memory Controller for Hard Real-Time CMPs, IEEE Embedded Systems Letters, vol. 1, no. 4. 2009.
J. Verdú, García, J., Nemirovsky, M., and Valero, M., Analysis of Traffic Traces for Statefull Applications. XV Jornadas de Paralelismo, 2004.
J. Verdú, García, J., Nemirovsky, M., and Valero, M., Analysis of Traffic Traces for Stateful Applications. NP3 : Third Workshop on Network Processors and Applications at HPCA-10, 2004.
K. Kedzierski, Cazorla, F., and Valero, M., Analysis of Simultaneous Multithreading Implementations in Current High-Performance Processors. ACACES 2006, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, 2006.
K. Kedzierski, Cazorla, F., and Valero, M., Analysis of multithreading capabilities of current high-performance processors. XVII Jornadas de Paralelismo, 2006.
O. J. Santana, Galluzzi, M., Ramirez, A., and Valero, M., An Analysis of Dynamic Instruction Streams, XIV Jornadas de Paralelismo. Leganés (Spain), pp. 527-532, 2003.
A. Falcón, Santana, O. J., Medina, P., Fernández, E., Ramirez, A., and Valero, M., An Analysis of Dynamic History Length Fitting, XII Jornadas de Paralelismo, Valencia (Spain). 2001.
M. March, García, J., Cerdá, L., and Valero, M., Analysis of a high performance DRAM/SRAM memory scheme for fast packet buffers. WEPA-1: Workshop on Embedded Parallel Architectures at HPCA-10, 2004.
A. García, Fernández, E., Medina, P., Ramirez, A., and Valero, M., Analisis y caracterización de los bucles, XIII Jornadas de Paralelismo. Lleida (Spain), 2002.
A. Pajuelo, González, A., and Valero, M., Aggressive Speculative Execution for Hidding Memory Latency. XV Jornadas de Paralelismo, 2004.
K. Kedzierski, Moreto, M., Cazorla, F., and Valero, M., Adapting Cache Partitioning Algorithms to Real pseudo-LRU Replacement Policies. In 24th IEEE International Parallel & Distributed Processing Symposium (IPDPS), Atlanta, Georgia, 2010.
B. Maric, Abella, J., and Valero, M., ADAM: An Efficient Data Management Mechanism for Hybrid High and Ultra-Low Voltage Operation Caches, ACM/IEEE Great Lakes Symposium on VLSI. ACM New York, NY, USA ©2012, Salt Lake City, United States, pp. 245–250, 2012.
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A. Vega, Ramirez, A., and Valero, M., 3D Die-Stacking Architectures: State of the Art, Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008. L'Aquila (Italy), pp. 203-207, 2008.

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