Publications

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A. Rico, Ramirez, A., and Valero, M., Available task-level parallelism on the Cell BE, Scientific Programming, vol. 17, no. 1-2. pp. 59-76, 2009.
V. Subotic, Ayguadé, E., Labarta, J., and Valero, M., Automatic Exploration of Potential Parallelism in Sequential Applications, 29th International Supercomputing Conference, ISC 2014. Springer, Leipzig, Germany, pp. 156–171, 2014.
F. Zyulkyarov, Gajinov, V., Unsal, O., Cristal, A., Ayguadé, E., Harris, T., and Valero, M., Atomic Quake: Using Transactional Memory in an Interactive Multiplayer Game Server, 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2009). ACM, Raleigh, North Carolina, United States, pp. 25–34, 2009.
R. González, Cristal, A., Pericàs, M., Valero, M., and Veidenbaum, A., An asymetric Clustered Processor Based on Value Content, The 19th ACM International Conference on Supercomputing (ICS'05). ACM Press, Boston, MA, United States, pp. 61–70, 2005.
M. Araya-Polo, Cabezas, J., Hanzich, M., Pericas, M., Morancho, E., Gelado, I., Shafiq, M., Rubio, F., Cela, J. M., Ayguadé, E., Navarro, N., and Valero, M., Assessing Accelerator-based HPC Reverse Time Migration, Transactions on Parallel and Distributed Systems, Special Issue on Accelerators, vol. 22(1). pp. 147-162, 2011.
R. González, Cristal, A., Ortega, D., and Valero, M., Arquitecturas Basadas en el Contenido, XIV Jornadas de Paralelismo. Leganés, Spain, pp. 541–546, 2003.
R. González, Cristal, A., Pericàs, M., Veidenbaum, A., and Valero, M., Arquitectura Simétrica Clusterizada basada en el Contenido, XVI Jornadas de Paralelismo. Thomson, Granada, Spain, 2005.
P. A. Castillo, Mora, A. M., Merelo, J. J., Laredo, J. L., Moreto, M., Cazorla, F., Valero, M., and McKee, S. A., Architecture performance prediction using evolutionary artificial neural networks. In European Workshop on Hardware Optimization Techniques (EVOHot). Napoli, Italy, 2008.
N. Markovic, González, R., Unsal, O., Valero, M., and Cristal, A., Architecture for Object-Oriented Programming Model. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, 2009.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A., and Valero, M., Architectural Support for Real-Time Task Scheduling in SMT Processors, International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES-2005). 2005.
E. Vallejo, Beivide, R., Cristal, A., Harris, T., Vallejo, F., Unsal, O., and Valero, M., Architectural Support for Fair Reader-Writer Locking, International Symposium on Microarchitecture. Atlanta, United States, 2010.
M. Valero, Verdú, J., Nemirovsky, M., and García, J., Architectural Impact of Statefull Networking APPlications. ANCS-2005. IEEE and ACM Symposium on Architectures for Networking and Communications Systems, 2005.
F. Cazorla, Fernández, E., Ramirez, A., and Valero, M., Approaching a Smart Sharing of Resources in SMT Processors, Workshop on Complexity-Effective Design (WCED). 2004.
B. Maric, Abella, J., and Valero, M., APPLE: Adaptive Performance-Predictable Low-Energy Caches for Reliable Hybrid Voltage Operation, 50th Annual Design Automation Conference (DAC). ACM, Austin (Texas), United States, pp. 1–6, 2013.
T. Hussain, Palomar, O., Unsal, O., Cristal, A., Ayguadé, E., Valero, M., and Rethinagiri, S. Kumar, APMC: Advanced Pattern based Memory Controller, 22nd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. ACM/SIGDA, Monterey, CA, United States, pp. 497-512, 2014.
B. Maric, Abella, J., and Valero, M., Analyzing the Efficiency of L1 Caches for Reliable Hybrid-Voltage Operation Using EDC Codes, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22. pp. 266-275, 2014.
M. Paolieri, Quiñones, E., Cazorla, F., and Valero, M., An Analyzable Memory Controller for Hard Real-Time CMPs, IEEE Embedded Systems Letters, vol. 1, no. 4. 2009.
J. Verdú, García, J., Nemirovsky, M., and Valero, M., Analysis of Traffic Traces for Statefull Applications. XV Jornadas de Paralelismo, 2004.
J. Verdú, García, J., Nemirovsky, M., and Valero, M., Analysis of Traffic Traces for Stateful Applications. NP3 : Third Workshop on Network Processors and Applications at HPCA-10, 2004.
K. Kedzierski, Cazorla, F., and Valero, M., Analysis of Simultaneous Multithreading Implementations in Current High-Performance Processors. ACACES 2006, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, 2006.
K. Kedzierski, Cazorla, F., and Valero, M., Analysis of multithreading capabilities of current high-performance processors. XVII Jornadas de Paralelismo, 2006.
O. J. Santana, Galluzzi, M., Ramirez, A., and Valero, M., An Analysis of Dynamic Instruction Streams, XIV Jornadas de Paralelismo. Leganés (Spain), pp. 527-532, 2003.
A. Falcón, Santana, O. J., Medina, P., Fernández, E., Ramirez, A., and Valero, M., An Analysis of Dynamic History Length Fitting, XII Jornadas de Paralelismo, Valencia (Spain). 2001.
M. March, García, J., Cerdá, L., and Valero, M., Analysis of a high performance DRAM/SRAM memory scheme for fast packet buffers. WEPA-1: Workshop on Embedded Parallel Architectures at HPCA-10, 2004.
A. García, Fernández, E., Medina, P., Ramirez, A., and Valero, M., Analisis y caracterización de los bucles, XIII Jornadas de Paralelismo. Lleida (Spain), 2002.
T. Hussain, Palomar, O., Cristal, A., Unsal, O., Ayguadé, E., and Valero, M., AMMC: Advanced Multi-core Memory Controller, 13th International Conference on Field Programmable Technology (FPT 2014). Shangai, China, 2014.
A. Pajuelo, González, A., and Valero, M., Aggressive Speculative Execution for Hidding Memory Latency. XV Jornadas de Paralelismo, 2004.
T. Hussain, Palomar, O., Unsal, O., Cristal, A., Ayguadé, E., and Valero, M., Advanced Pattern based Memory Controller for FPGA based HPC Applications, International Conference on High Performance Computing {&} Simulation, HPCS 2014. IEEE, Bologna, Italy, pp. 287–294, 2014.
D. Prat, Ortega, C., Casas, M., Moreto, M., and Valero, M., Adaptive and application dependent runtime guided hardware prefetcher reconfiguration on the IBM POWER7, 6th International Workshop on Adaptive Self-tuning Computing Systems. arXiv.org, Amsterdam, Netherlands, pp. 1–6, 2015.
K. Kedzierski, Moreto, M., Cazorla, F., and Valero, M., Adapting Cache Partitioning Algorithms to Real pseudo-LRU Replacement Policies. In 24th IEEE International Parallel & Distributed Processing Symposium (IPDPS), Atlanta, Georgia, 2010.
B. Maric, Abella, J., and Valero, M., ADAM: An Efficient Data Management Mechanism for Hybrid High and Ultra-Low Voltage Operation Caches, ACM/IEEE Great Lakes Symposium on VLSI. ACM New York, NY, USA ©2012, Salt Lake City, United States, pp. 245–250, 2012.
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A. Vega, Ramirez, A., and Valero, M., 3D Die-Stacking Architectures: State of the Art, Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008. L'Aquila (Italy), pp. 203-207, 2008.

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