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K. Kedzierski, Moreto, M., Cazorla, F., and Valero, M., Adapting Cache Partitioning Algorithms to Real pseudo-LRU Replacement Policies. In 24th IEEE International Parallel & Distributed Processing Symposium (IPDPS), Atlanta, Georgia, 2010.
B. Maric, Abella, J., and Valero, M., ADAM: An Efficient Data Management Mechanism for Hybrid High and Ultra-Low Voltage Operation Caches, ACM/IEEE Great Lakes Symposium on VLSI. ACM New York, NY, USA ©2012, Salt Lake City, United States, pp. 245–250, 2012.
A. Vega, Ramirez, A., and Valero, M., 3D Die-Stacking Architectures: State of the Art, Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008. L'Aquila (Italy), pp. 203-207, 2008.