Publications

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T. Hussain, Palomar, O., Unsal, O., Cristal, A., Ayguadé, E., and Valero, M., PVMC: Programmable Vector Memory Controller, IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2014). IEEE, Zurich, Switzerland, pp. 240–247, 2014.
K. Kedzierski, Moreto, M., Cazorla, F., and Valero, M., pseudo-LRU based Cache Partitioning Algorithms. In International Symposium on Parallel Architectures and Compilation Techniques, North Carolina, USA, 2009.
A. Falcón, Stark, J., Ramirez, A., Lai, K., and Valero, M., Prophet/Critic Hybrid Branch Prediction, 31st Annual International Symposium on Computer Architecture (ISCA-31). pp. 250-262, 2004.
V. Subotic, Brinkmann, S., Marjanovic, V., Badia, R. M., Gracia, J., Niethammer, C., Ayguadé, E., Labarta, J., and Valero, M., Programmability and portability for exascale: Top down programming methodology and tools with StarSs, Journal of Computational Science, vol. 4. pp. 450–456, 2013.
N. Sönmez, Cristal, A., Unsal, O., Harris, T., and Valero, M., Profiling Transactional Memory applications on an Atomic Block Basis: A Haskell case study, Second Workshop on Programmability Issues for Multi-Core Computers (MULTIPROG 2009). Paphos, Cyprus, 2009.
S. Stipic, Smiljkovi, V., Unsal, O., Cristal, A., and Valero, M., Profile-Guided Transaction Coalescing—Lowering Transactional Overheads by Merging Transactions, ACM Transactions on Architecture and Code Optimization 2014. Vienna, Austria, 2014.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A., and Valero, M., On the Problem of Minimizing Workload Execution Time in SMT Processors, International Conference on Embedded Computer Systems: Architectures, Modelling, and Simulation (SAMOS VII). Samos, Greece, pp. 66-73, 2007.
F. Cazorla, Pajuelo, A., Santana, O. J., Fernandez, E., and Valero, M., On the Problem of Evaluating the Performance of Multiprogrammed Workloads. , IEEE Transactions on Computers, vol. 59, no. 12. IEEE, 2010.
S. Isaza, Sánchez, F., Gaydadjiev, G. N., Ramirez, A., and Valero, M., Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications, Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS'08). pp. 53-64, 2008.
O. J. Santana, Ramirez, A., and Valero, M., Predicting two Streams per Cycle, XVI Jornadas de Paralelismo. pp. 3-10, 2005.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A., and Valero, M., Predictable Performance in SMT processors: Synergy Between the OS and SMTs, IEEE Transactions on Computers, vol. 55, no. 7. pp. 785-799, 2006.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A., and Valero, M., Predictable Performance in SMT Processors, Computing Frontiers (CF'04). 2004.
V. J. Jiménez, Boneti, C., Cazorla, F., Gioiosa, R., Kursun, E., Cher, C. - Y., Isci, C., Buyuktosunoglu, A., Bose, P., and Valero, M., Power and Thermal Characterization of POWER6 System. The 19th International Conference on Parallel Architectures and Compilation Techniques (PACT), 2010.
K. Kedzierski, Cazorla, F., Gioiosa, R., Buyuktosunoglu, A., and Valero, M., Power and Performance Aware Reconfigurable Cache for CMPs. Workshop on Next Generation Multicore/Manycore Technologies (IFMT), in conjunction with ISCA, 2010.
M. Pericas, Ayguadé, E., Zalamea, J., Llosa, J., and Valero, M., Power and Performace Evaluation of Widened and Clustered VLIW Cores. LNCS, 2005.
Ivan Ratkovic, Palomar, O., Milan Stanic,, Unsal, O., Cristal, A., and Valero, M., Physically vs. Physically-Aware Estimation Flow: Case Study of Design Space Exploration of Adders, IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, Tampa, Florida, United States, pp. 118–123, 2014.
T. Morad, Weiser, U., Kolodny, A., Valero, M., and Ayguadé, E., Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors. IEEE CAL, Computer Architecture Letters, 2006.
C. Navarro, Ramirez, A., Larriba-Pey, J. L., and Valero, M., On the Performance of Fetch Engines Running DSS Workloads, 6th International Euro-Par Conference (EuroPar'2000). Springer-Verlag, pp. 591-595, 2000.
M. Álvarez, Salami, E., Labarta, J., and Valero, M., Performance Impact of Unaligned memory Operations in SIMD Extensions for Video CODEC Applications, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2007). San José, California, USA., pp. 62-71, 2007.
A. Ramirez, Prat, O., Labarta, J., and Valero, M., Performance Impact of the Interconnection Network on MareNostrum Applications, 1st Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC 2007). 2007.
M. Álvarez, Ramirez, A., Valero, M., Azevedo, A., Meenderinck, C., and Juurlink, B., Performance Evaluation of Macroblock-level Parallelization of H.264 Decoding on a cc-NUMA Multiprocessor Architecture, 4CCC. 4th Colombian Computing Conference, Bucaramanga (Colombia). 2010.
M. Álvarez, Ramirez, A., Valero, M., Azevedo, A., Meenderinck, C., and Juurlink, B., Performance Evaluation of Macroblock-level Parallelization of H.264 Decoding on a cc-NUMA Multiprocessor Architecture, Avances en Sistemas e Informática, vol. 6, no. 1. pp. 219-228, 2009.
M. Álvarez, Salami, E., Ramirez, A., and Valero, M., A Performance Evaluation of High Definition Digital Video Decoding Using the H.264/AVC Standard, ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. pp. 255-258, 2005.
M. Álvarez, Salami, E., Ramirez, A., and Valero, M., A Performance Characterization of High Definition Digital Video Decoding Using H.264/AVC, 2005 IEEE International Symposium on Workload Characterization (IISWC-2005). IEEE Computer Society Press, pp. 24-33, 2005.
M. Pericas, Ayguadé, E., Zalamea, J., Llosa, J., and Valero, M., Performance and Power Evaluation of Clustered VLIW Processors with Functional Units. Lecture Notes on Computer Science, 2004.
F. Sánchez, Salami, E., Ramirez, A., and Valero, M., Performance Analysis of Sequence Alignment Applications, IISWC, IEEE Internacional Symposium on Workload Characterization. 2006.
R. Holanda, Verdú, J., García, J., and Valero, M., Performance Analysis of New Packet Trace Compression TCP Flow Clustering. ISPASS05. IEEE International Symposium on Performance Analisys of Systems and Software, 2005.
M. A. Ramírez, Cristal, A., Valero, M., Veidenbaum, A., and Villa, L. A., A partitioned instruction queue to reduce instruction wakeup energy, International Journal of High Performance Computing and Networking, vol. 1, pp. 153–161, 2004.
S. Isaza, Sánchez, F., Gaydadjiev, G. N., Ramirez, A., and Valero, M., Parameterizing Multicore Architectures for Multiple Sequence Alignment, 2011 International Conference on Computing Frontiers. 2011.
F. Sánchez, Ramirez, A., and Valero, M., Parallelization Strategies for Smith Waterman Algorithm on CellBE, Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008, Poster Session. L'Aquila (Italy), 2008.
E. Salami, Ramirez, A., Sánchez, F., and Valero, M., Parallel Processing in Sequence Matching, ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. 2005.
F. Sánchez, Salami, E., Ramirez, A., and Valero, M., Parallel Processing in Biological Sequence Comparison using General Purpose Processors, 2005 IEEE International Symposium on Workload Characterization (IISWC-2005). 2005.
A. Azevedo, Meenderinck, C., Juurlink, B., Terechko, A., Hoogerbrugge, J., Álvarez, M., Ramirez, A., and Valero, M., Parallel H.264 Decoding on an Embedded Multicore Processor, 4th International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC'09). pp. 404-418, 2009.
T. Hussain, Sönmez, N., Palomar, O., Unsal, O., Cristal, A., Ayguadé, E., and Valero, M., PAMS: Pattern Aware Memory System for Embedded Systems, ReConFig - International Conference on ReConFifurable Computing and FPGAs. Cancun, Mexico, 2014.