Publications

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Kedzierski, K., Moreto, M., Cazorla, F. & Valero, M. pseudo-LRU based Cache Partitioning Algorithms. (2009).
Falcón, A., Stark, J., Ramirez, A., Lai, K. & Valero, M. Prophet/Critic Hybrid Branch Prediction. 31st Annual International Symposium on Computer Architecture (ISCA-31) 250-262 (2004).
Subotic, V. et al. Programmability and portability for exascale: Top down programming methodology and tools with StarSs. Journal of Computational Science 4, 450–456 (2013).
Sönmez, N., Cristal, A., Unsal, O., Harris, T. & Valero, M. Profiling Transactional Memory applications on an Atomic Block Basis: A Haskell case study. Second Workshop on Programmability Issues for Multi-Core Computers (MULTIPROG 2009) (2009).
Cazorla, F. et al. On the Problem of Minimizing Workload Execution Time in SMT Processors. International Conference on Embedded Computer Systems: Architectures, Modelling, and Simulation (SAMOS VII) 66-73 (2007). at <http://dx.doi.org/10.1109/ICSAMOS.2007.4285735>
Cazorla, F., Pajuelo, A., Santana, O. J., Fernandez, E. & Valero, M. On the Problem of Evaluating the Performance of Multiprogrammed Workloads. . IEEE Transactions on Computers 59, (2010).
Isaza, S., Sánchez, F., Gaydadjiev, G. N., Ramirez, A. & Valero, M. Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications. Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS'08) 53-64 (2008).
Santana, O. J., Ramirez, A. & Valero, M. Predicting two Streams per Cycle. XVI Jornadas de Paralelismo 3-10 (2005).
Cazorla, F. et al. Predictable Performance in SMT processors: Synergy Between the OS and SMTs. IEEE Transactions on Computers 55, 785-799 (2006).
Cazorla, F. et al. Predictable Performance in SMT Processors. Computing Frontiers (CF'04) (2004).
Jiménez, V. J. et al. Power and Thermal Characterization of POWER6 System. (2010).
Kedzierski, K., Cazorla, F., Gioiosa, R., Buyuktosunoglu, A. & Valero, M. Power and Performance Aware Reconfigurable Cache for CMPs. (2010).
Pericas, M., Ayguadé, E., Zalamea, J., Llosa, J. & Valero, M. Power and Performace Evaluation of Widened and Clustered VLIW Cores. (2005).
Morad, T., Weiser, U., Kolodny, A., Valero, M. & Ayguadé, E. Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors. (2006).
Navarro, C., Ramirez, A., Larriba-Pey, J. L. & Valero, M. On the Performance of Fetch Engines Running DSS Workloads. 6th International Euro-Par Conference (EuroPar'2000) 591-595 (2000).
Álvarez, M., Salami, E., Labarta, J. & Valero, M. Performance Impact of Unaligned memory Operations in SIMD Extensions for Video CODEC Applications. IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2007) 62-71 (2007).
Ramirez, A., Prat, O., Labarta, J. & Valero, M. Performance Impact of the Interconnection Network on MareNostrum Applications. 1st Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC 2007) (2007).
Álvarez, M. et al. Performance Evaluation of Macroblock-level Parallelization of H.264 Decoding on a cc-NUMA Multiprocessor Architecture. Avances en Sistemas e Informática 6, 219-228 (2009).
Álvarez, M. et al. Performance Evaluation of Macroblock-level Parallelization of H.264 Decoding on a cc-NUMA Multiprocessor Architecture. 4CCC. 4th Colombian Computing Conference, Bucaramanga (Colombia) (2010).
Álvarez, M., Salami, E., Ramirez, A. & Valero, M. A Performance Evaluation of High Definition Digital Video Decoding Using the H.264/AVC Standard. ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems 255-258 (2005).
Álvarez, M., Salami, E., Ramirez, A. & Valero, M. A Performance Characterization of High Definition Digital Video Decoding Using H.264/AVC. 2005 IEEE International Symposium on Workload Characterization (IISWC-2005) 24-33 (2005).
Pericas, M., Ayguadé, E., Zalamea, J., Llosa, J. & Valero, M. Performance and Power Evaluation of Clustered VLIW Processors with Functional Units. (2004).
Sánchez, F., Salami, E., Ramirez, A. & Valero, M. Performance Analysis of Sequence Alignment Applications. IISWC, IEEE Internacional Symposium on Workload Characterization (2006).
Holanda, R., Verdú, J., García, J. & Valero, M. Performance Analysis of New Packet Trace Compression TCP Flow Clustering. (2005).
Ramírez, M. A., Cristal, A., Valero, M., Veidenbaum, A. & Villa, L. A. A partitioned instruction queue to reduce instruction wakeup energy. International Journal of High Performance Computing and Networking 1, 153–161 (2004).
Isaza, S., Sánchez, F., Gaydadjiev, G. N., Ramirez, A. & Valero, M. Parameterizing Multicore Architectures for Multiple Sequence Alignment. 2011 International Conference on Computing Frontiers (2011).
Sánchez, F., Ramirez, A. & Valero, M. Parallelization Strategies for Smith Waterman Algorithm on CellBE. Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008, Poster Session (2008).
Salami, E., Ramirez, A., Sánchez, F. & Valero, M. Parallel Processing in Sequence Matching. ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems (2005).
Sánchez, F., Salami, E., Ramirez, A. & Valero, M. Parallel Processing in Biological Sequence Comparison using General Purpose Processors. 2005 IEEE International Symposium on Workload Characterization (IISWC-2005) (2005).
Azevedo, A. et al. Parallel H.264 Decoding on an Embedded Multicore Processor. 4th International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC'09) 404-418 (2009).