Publications

Export 15 results:
Author [ Title(Asc)] Type Year
Filters: Author is Mateo Valero and First Letter Of Title is M  [Clear All Filters]
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 
M
M. Milovanovic, Ferrer, R., Gajinov, V., Unsal, O., Cristal, A., Ayguadé, E., and Valero, M., Multithreaded software transactional memory and OpenMP, 8th MEDEA Workshop Memory Performance: Dealing With Applications, Systems And Architecture (MEDEA 2007). ACM, Brasov, Romania, pp. 81–88, 2007.
I. González, Galluzzi, M., Cristal, A., and Valero, M., Multi-State Processor: Arquitectura sin ROB y con recuperaciones Precisas, II Congreso Español de Informática (CEDI 2007). Zaragoza, Spain, 2007.
I. González, Galluzzi, M., Cristal, A., and Valero, M., The Multi-State Processor, 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07). Academia Press, L'Aquila, Italy, pp. 127–130, 2007.
O. J. Santana, Ramirez, A., and Valero, M., Multiple Stream Prediction, ISHPC. International Symposium on High Performance Computers. Springer-Verlag, 2005.
K. J. Nesbit, Moreto, M., Cazorla, F., Ramirez, A., Valero, M., and Smith, J. E., Multicore Resource Management, IEEE Micro, vol. 28, no. 3. pp. 6-16, 2008.
M. Moreto, Cazorla, F., Ramirez, A., and Valero, M., MLP-aware dynamic cache partitioning, 2008 International Conference on High Performance Embedded Architectures & Compilers (HiPEAC 2008). Goteborg, Sweden, pp. 337-352, 2008.
M. Moreto, Cazorla, F., Ramirez, A., and Valero, M., MLP-aware dynamic cache partitioning, International Conference on Parallel Architectures and Compilation Techniques (PACT). Brasov, Romania, pp. 418-418, 2007.
J. J. Alastruey, Monreal, T., Viñals, V., and Valero, M., Microarchitectural Support for Speculative Register Renaming. IPDPS07. IEEE International Parallel and Distributed Processing Sympsium. Long Beach, USA, 2006.
C. Acosta, Cazorla, F., Ramirez, A., and Valero, M., MFLUSH: Handling Long-latency loads in SMT On-Chip Multiprocessors., International Conference on Parallel Processing (ICPP). pp. 173-181, 2008.
S. Mir, Cazorla, F., Ramirez, A., and Valero, M., Metrics for the Evaluation of SMT Processors Performance, XVI Jornadas de Paralelismo. 2005.
F. Zyulkyarov, Unsal, O., Cristal, A., Milovanovic, M., Ayguadé, E., and Valero, M., Memory Management for Transaction Processing Core in Heterogeneous Chip Multiprocessors, Workshop on Operating System Support for Heterogeneous Multicore Architectures. Brasov, Romania, 2007.
J. Vera, Cazorla, F., Pajuelo, A., Santana, O. J., Fernández, E., and Valero, M., Measuring the Performance of Multithreaded Processors. In SPEC Benchmark Workshop (in conjunction with the Annual Meeting of the Standard Performance Evaluation Corporation (SPEC)), Austin, USA, 2007.
P. Radojkovic, Cakarevic, V., Verdú, J., Pajuelo, A., Gioiosa, R., Cazorla, F., Nemirovsky, M., and Valero, M., Measuring Operating System Overhead on CMT Processors. In 20th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). Campo Grande, Brazil, 2008.
T. Hussain, Palomar, O., Unsal, O., Cristal, A., Ayguadé, E., and Valero, M., MAPC. Memory Access Pattern based Controller, 24th International Conference on Field Programmable Logic and Applications (FPL), 2014. IEEE, Munich, Germany, pp. 1–4, 2014.
A. Cristal, Santana, O. J., and Valero, M., Maintaining Thousands of In-Flight Instructions, 10th International Euro-Par 2004 Conference. Springer-Verlag, Pisa, Italy, pp. 9–20, 2004.