Export 14 results:Author [ Title] Type Year
Filters: Author is Mateo Valero and First Letter Of Title is L [Clear All Filters]
A Low-Power-Instruction-Queue Wakeup Mechanism. XIV Jornadas de Paralelismo 533–540 (2003).
A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors. 10th International Conference on High Performance Computer Architecture (HPCA-10) 244-253 (2004).
A Low-Complexity Fetch Architecture for High-Performance Superscalar Processors. ACM Transactions on Architecture and Code Optimization 1, 220-245 (2004).
A Low Complexity Fetch Architecture for High Performance Superscalar Processors. ACM Transactions on Architecture and Compiler Optimizations (TACO) 1, 220-245 (2004).
Long DNA Sequence Comparison on Multicore Architectures. 16th international Euro-Par conference on Parallel processing (2010). at <http://dx.doi.org/10.1007/978-3-642-15291-7_24>
The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment. Computing Frontiers '08 67–78 (2008).
The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment. 5th Conference on Computing Frontiers 67–78 (ACM, 2008). at <http://capinfo.e.ac.upc.edu/PDFs/dir06/file003457.pdf>
Latency Tolerant Branch Predictors. 2003 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'03) 30-39 (2003).
A latency conscious SMT branch predictor architecture. International Journal of High Performance Computing and Networking (IJHPCN) 2, 11-21 (2004).