Publications

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Ramírez, M. A., Cristal, A., Veidenbaum, A., Villa, L. A. & Valero, M. A Low-Power-Instruction-Queue Wakeup Mechanism. XIV Jornadas de Paralelismo 533–540 (2003).
Falcón, A., Ramirez, A. & Valero, M. A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors. 10th International Conference on High Performance Computer Architecture (HPCA-10) 244-253 (2004).
Santana, O. J., Ramirez, A., Larriba-Pey, J. L. & Valero, M. A Low-Complexity Fetch Architecture for High-Performance Superscalar Processors. ACM Transactions on Architecture and Code Optimization 1, 220-245 (2004).
Valero, M., Santana, O. J., Ramirez, A. & Larriba-Pey, J. L. A Low Complexity Fetch Architecture for High Performance Superscalar Processors. ACM Transactions on Architecture and Compiler Optimizations (TACO) 1, 220-245 (2004).
Vera, J. et al. Looking for novel ways to obtain fair measurements in multithreaded architectures. (2006).
Sánchez, F., Cabarcas, F., Ramirez, A. & Valero, M. Long DNA Sequence Comparison on Multicore Architectures. 16th international Euro-Par conference on Parallel processing (2010). at <http://dx.doi.org/10.1007/978-3-642-15291-7_24>
Moreto, M., Cazorla, F., Sakellariou, R. & Valero, M. Load Balancing Using Dynamic Cache Allocation. (2010).
Alastruey, J. J., Monreal, T., Viñals, V. & Valero, M. Limits on Early Release of Physical Registers. (2004).
Perfumo, C. et al. The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment. 5th Conference on Computing Frontiers 67–78 (ACM, 2008). at <http://capinfo.e.ac.upc.edu/PDFs/dir06/file003457.pdf>
Perfumo, C. et al. The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment. Computing Frontiers '08 67–78 (2008).
Santana, O. J., Ramirez, A. & Valero, M. Latency Tolerant Branch Predictors. 2003 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'03) 30-39 (2003).
Falcón, A., Santana, O. J., Ramirez, A. & Valero, M. A latency conscious SMT branch predictor architecture. International Journal of High Performance Computing and Networking (IJHPCN) 2, 11-21 (2004).
Monreal, T., Viñals, V., González, J., González, A. & Valero, M. Late Allocation and Early Release of Physical Registers. (2004).
Cristal, A., Valero, M., González, A. & Llosa, J. Large Virtual ROBs by Processor Checkpointing. (2002). at <http://capinfo.e.ac.upc.edu/PDFs/dir11/file000939.pdf>