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Filters: Author is Mateo Valero and First Letter Of Title is F [Clear All Filters]
Future ILP processors. International Journal of High Performance Computing and Networking 2, 1–10 (2004).
From plasma to beefarm: Design experience of an FPGA-based multicore prototype. Reconfigurable Computing: Architectures, Tools and Applications 350–362 (2011).
From Plasma to BeeFarm: Design Experience of an FPGA-based Multicore Prototype. The 7th International Symposium on Applied Reconfigurable Computing (ARC 2011) 1–10 (2011).
A Flexible Hybrid Transactional Memory Multicore on FPGA. Jornadas de Paralelismo 2011 283–289 (2011).
A Flexible Heterogeneous Multi-Core Architecture. The 2007 International Conference on Parallel Architectures and Compilation Techniques (PACT 2007) 13–24 (2007). at <http://capinfo.e.ac.upc.edu/PDFs/dir10/file003258.pdf>
FlexDCP: a QoS framework for CMP architectures. ACM Operating Systems Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors 43, 86-96 (2010).
FlexDCP: a QoS framework for CMP architectures. ACM SIGOPS Operating System Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors 43, 0163-5980 (2009).
A First Glance at the Implementation of Precise Recoveries in Out-of-order Commit Processors. (2006).
A first glance at Kilo-instruction based multiprocessors. International Conference on Computing Frontiers 2004 (CF'04) 212–221 (ACM Press, 2004). at <http://capinfo.e.ac.upc.edu/PDFs/dir20/file002978.pdf>
FIMSIM: A fault injection infrastructure for microarchitectural simulators. 29th International Conference on Computer Design (ICCD) 431–432 (2011).
Fetching Instruction Streams. 35th Annual International Symposium on Microarchitecture (MICRO-35) 371-382 (2002).
Fetch Engines and Databases. 3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3) (2000).
Feasibility of QoS for SMT by Resource Allocation. Lecture Notes in Computer Science (LNCS) 3149/2004, (2004).
FaulTM-multi: Fault Tolerance for Multithreaded Applications Running on Transactional Memory Hardware. Workshop on Wild and Sane Ideas in Speculation and Transactions (2011).
FAME: FAirly MEasuring Multithreaded Architectures. (2007). at <http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4336221>
Fair CPU Time Accounting in CMP+SMT Processors. ACM Trans. Archit. Code Optim. 9, 50:1–50:25 (2013).