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WormBench: a configurable workload for evaluating transactional memory systems. 9th workshop on MEmory performance: DEaling with Applications, systems and architecture (MEDEA 2008) 61–68 (ACM, 2008). at <http://capinfo.e.ac.upc.edu/PDFs/dir21/file003646.pdf>
User-directed Auto-vectorization in OmpSs. ACACES 2011. Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems (2011). at <http://www.hipeac.net/summerschool>
Unrolling Loops Containing Task Parallelism. (2009). at <http://nanos.ac.upc.edu/content/unrolling-loops-containing-task-parallelism>
Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions. 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2009) 307–308 (ACM, 2009).
Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions. ACM SIGPLAN Notices 44, 307–308 (2009).
Tuning Dynamic Web Applications using Fine-Grain Analysis. 13th Euromicro Conference on Parallel, Distributed and Network-based Processing (PDP'05) 84-91 (2005). doi:http://dx.doi.org/10.1109/EMPDP.2005.44
Transient Congestion Avoidance in Software Distributed Shared Memory Systems. (2010). at <http://doi.ieeecomputersociety.org/10.1109/PDCAT.2010.32>
Transactional Memory and OpenMP. International Workshop on OpenMP (IWOMP-2007) 37–53 (Springer-Verlag, 2007). at <http://capinfo.e.ac.upc.edu/PDFs/dir05/file003195.pdf>
Transactional Memory: An Overview. IEEE Micro 27, 8–29 (2007).
Transactional Access to Shared Memory in StarSs, a Task Based Programming Model. 18th International Conference, Euro-Par 2012 514–525 (2012).
A Template System for the Efficient Compilation of Domain Abstractions onto Reconfigurable Computers. 5th HiPEAC Workshop on Reconfigurable Computing (WRC 2011) 65–74 (2011).
Task Superscalar: Using Processors as Functional Units. USENIX Workshop on Hot Topics In Parallelism (HotPar) (2010).
Task Superscalar: An Out-of-Order Task Pipeline. IEEE/ACM Intl. Symp. on Microarchitecture (MICRO-43) 89-100 (2010). at <http://dx.doi.org/10.1109/MICRO.2010.13>
TARCAD: A template architecture for reconfigurable accelerator designs. IEEE Symposium on Application Specific Processors (SASP) 8-15 (2011).
Tailoring resources: the energy-efficient consolidation strategy, goes beyond virtualization. 5th IEEE International Conference on Autonomic Computing (ICAC 2008) (Poster Paper) 197-198 (2008). doi:http://dx.doi.org/10.1109/ICAC.2008.11
A Systematic Methodology to Generate Decomposable and Responsive Power Models for CMPs. Computers, IEEE Transactions on PP, 1 (2012).
A Survey on Performance Management for Internet Applications. Concurrency and Computation: Practice and Experience Vol. 22 (1), 68-106 (2010).
Supporting Stateful Tasks in a Dataflow Graph. Proceedings of the 21st international conference on Parallel architectures and compilation techniques 435–436 (2012).
A Streaming Machine Description and Programming Model. 7th Intl. Workshop on Embedded Computer Systems: Architectures, MOdeling, and Simulation (SAMOS VII) 107-116 (2007).
Strategies for Efficient Exploitation of Loop-Level Parallelism in Java Concurrency and Computation. Concurrency and Computation: Practice and Experience Vol. 13 (8-9), 663-680 (2001).
Starsscheck: a tool to find errors in task-based parallel programs. 16th international Euro-Par conference on Parallel processing 2-13 (2010). at <http://portal.acm.org/citation.cfm?id=1887695.1887698>
Software-Managed Power Reduction in Infiniband Links. ICPP 2014 (2014).
Simulating complex systems with a low-detail model. XVI Jornadas de Paralelismo 301-308 (2005). at <http://www.bsc.es/media/383.pdf>
Session-Based Adaptative Overload Control for Secure Dynamic Web Application. 34th International Conference on Parallel Processing (ICPP-05) 341-349 (2005). doi:http://dx.doi.org/10.1109/ICPP.2005.72
Self-Adaptive OmpSs Tasks in Heterogeneous Environments. The 27th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2013) 138–149 (2013). doi:10.1109/IPDPS.2013.53
Scalability of Macroblock-level Parallelism for H.264 Decoding. Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008, Poster 59-62 (2008).
Runtime-Aware Architectures: A First Approach. International Journal on Supercomputing Frontiers and Innovations 1, 29-44 (2014).
Resource-aware Adaptive Scheduling for MapReduce Clusters. ACM/IFIP/USENIX 12th International Middleware Conference (Middleware 2011) (2011).
Reducing Data Access Latency in SDSM Systems using Runtime Optimizations. 19th Annual International Conference hosted by the Centre for Advanced Studies & Research (CASCON 2010) 160-173 (2010). doi:10.1145/1923947.1923965
Reconfigurable Memory Controller with Programmable Pattern Support. 5th HiPEAC Workshop on Reconfigurable Computing (WRC 2011) 55–64 (2011).
QuakeTM: parallelizing a complex sequential application using transactional memory. Proceedings of the 23rd international conference on Supercomputing 126–135 (2009).
QuakeTM: parallelizing a complex sequential application using transactional memory. 23rd international conference on Supercomputing (ICS 2009) 126–135 (ACM, 2009). at <http://capinfo.e.ac.upc.edu/PDFs/dir21/file003443.pdf>