Publications

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2016
J. Jalle, Fernández, M., Abella, J., Andersson, J., Patte, M., Fossati, L., Zulianello, M., and Cazorla, F., Bounding Resource-Contention Interference in the Next-Generation Multipurpose Processor (NGMP), 8th European Congress on Embedded Real Time Software and Systems (ERTS^2). 2016.
M. Riera Villanueva, Canal, R., Abella, J., and González, A., A Detailed Methodology to Soft Error Rates in Advanced Technologies, In Proceedings of the Design Automation and Test in Europe (DATE) Dresden, Germany. 2016.
M. Panic, Hernandez, C., Abella, J., Perez, A. Roca, Quiñones, E., and Cazorla, F., Improving Performance Guarantees in Wormhole Mesh NoC Designs, In Proceedings of the Design Automation and Test in Europe (DATE) Dresden, Germany. 2016.
S. Kehr, Panic, M., Quiñones, E., Boeddeker, B., Sandoval, J. Becerril, Abella, J., Cazorla, F., and Schäfer, G., Maximizing Runnable-level Parallelism in AUTOSAR Applications, In Proceedings of the Design Automation and Test in Europe (DATE) Dresden, Germany. 2016.
M. Panic, Hernandez, C., Quiñones, E., Abella, J., and Cazorla, F., Modeling High-Performance Wormhole NoCs for Critical Real-Time Embeddedd Systems, 22nd IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), Viena, Austria. 2016.
Q. Liu, Moreto, M., Abella, J., Cazorla, F., Jiménez, D. A., and Valero, M., Sensible Energy Accounting with Abstract Metering for Multicore Systems, 11th International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC). 2016.
2015
J. Espinosa, Hernandez, C., Abella, J., De Andres, D., and Ruiz, J. Carlos, Analysis and RTL Correlation of Instruction Set Simulators for Automotive Microcontroller Robustness Verification, Design Automation Conference (DAC) San Francisco, CA. 2015.
M. Panic, Quiñones, E., Hernandez, C., Abella, J., and Cazorla, F., CAP: Communication-aware Allocation Algorithm for Real-Time Parallel Applications on Many-cores , 18th Euromicro Conference on Digital System Design (DSD) Madeira, Portugal. 2015.
J. Espinosa, Hernandez, C., and Abella, J., Characterizing Fault Propagation in Safety-Critical Processor Designs, 21st IEEE International On-Line Testing Symposium (IOLTS), Elia, Halkidiki, Greece. 2015.
M. Panic, Abella, J., Hernandez, C., Quiñones, E., Ungerer, T., and Cazorla, F., Enabling TDMA Arbitration in the Context of MBPTA , 18th Euromicro Conference on Digital System Design (DSD) Madeira, Portugal. 2015.
M. Ziccardi, Mezzetti, E., Vardanega, T., Abella, J., and Cazorla, F., EPC: Extended Path Coverage for Measurement-based Probabilistic Timing Analysis, IEEE Real-Time Systems Symposium (RTSS) San Antonio, Texas. 2015.
T. Ungerer, Bradatsch, C., Frieb, M., Kluge, F., Mische, J., Stegmeier, A., Jahr, R., Gerdes, M., Zaykov, P., Matusova, L., Li, Z. Jian Jia, Petrov, Z., Boddeker, B., Kehr, S., Regler, H., Hugl, A., Roc, C., Ozaktas, H., Casse, H., Bonenfant, A., Sainrat, P., Lay, N., George, D., Broster, I., Quiñones, E., Panic, M., Abella, J., Hernandez, C., Cazorla, F., Uhrig, S., Rohde, M., and Pyka, A., Experiences and Results of Parallelisation of Industrial Hard Real-time Applications for the parMERASA Multi-core, 3rd Workshop on High-performance and Real-time Embedded Systems (HiRES), Amsterdam, The Netherlands. 2015.
J. Abella, del Castillo, J., Cazorla, F., and Padilla, M., Extreme value theory in computer sciences: The case of embedded safety-critical systems, 6th International Conference on Risk Analysis (ICRA). 2015.
I. Agirre, Azkarate-askasua, M., Perez, J., Hernandez, C., Abella, J., Vardanega, T., and Cazorla, F., IEC-61508 SIL 3-compliant Pseudo-Random Number Generators for Probabilistic Timing Analysis , 18th Euromicro Conference on Digital System Design (DSD) Madeira, Portugal. 2015.
G. Fernandez, Jalle, J., Abella, J., Quiñones, E., Vardanega, T., and Cazorla, F., Increasing Confidence on Measurement-Based Contention Bounds for Real-Time Round-Robin Buses, Design Automation Conference (DAC) San Francisco, CA. 2015.
G. Fernandez, Abella, J., Quiñones, E., Fossati, L., Zulianello, M., Vardanega, T., and Cazorla, F., Introduction to Partial Time Composability for COTS Multicores, 230th ACM/SIGAPP Symposium On Applied Computing (SAC). 2015.
C. Hernandez and Abella, J., Low-cost Checkpointing in Automotive Safety-Relevant Systems, 18th Design, Automation and Test in Europe Conference (DATE), Grenoble, France . 2015.
S. Milutinovic, Quiñones, E., Abella, J., and Cazorla, F., PACO: Fast Average-Performance Estimation for Time-Randomized Caches , Design Automation Conference (DAC) San Francisco, CA. 2015.
E. Mezzetti, Ziccardi, M., Vardanega, T., Abella, J., Quiñones, E., and Cazorla, F., Randomized Caches Can Be Pretty Useful to Hard Real-Time Systems , Leibniz Transactions on Embedded Systems (LITES), vol. 2. 2015.
G. Fernandez, Jalle, J., Abella, J., Quiñones, E., Vardanega, T., and Cazorla, F., Resource Usage Templates and Signatures for COTS Multicore Processors, Design Automation Conference (DAC) San Francisco, CA. 2015.
G. Fernandez, Abella, J., Quiñones, E., Fossati, L., Zulianello, M., Vardanega, T., and Cazorla, F., Seeking Time-Composable Partitions of Tasks for COTS Multicore Processors, IEEE 18th International Symposium on Real-Time Distributed Computing, (ISORC) Auckland, New Zealand. 2015.
S. Milutinovic, Abella, J., Hardy, D., Quiñones, E., Puaut, I., and Cazorla, F., Speeding up Static Probabilistic Timing Analysis, 28th GI/ITG International Conference on Architecture of Computing Systems (ARCS). 2015.
C. Hernandez and Abella, J., Timely Error Detection for Effective Recovery in Light-Lockstep Automotive Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 34, no. 11. pp. 1718-1729, 2015.
F. Wartel, Kosmidis, L., Gogonel, A., Baldovin, A., Stephenson, Z., Triquet, B., Quiñones, E., Lo, C., Mezzetti, E., Broster, I., Abella, J., Cucu-Grosjean, L., Vardanega, T., and Cazorla, F., Timing Analysis of an Avionics Case Study on Complex Hardware/Software Platforms, 18th Design, Automation and Test in Europe Conference (DATE). 2015.
J. Espinosa, De Andres, D., Ruiz, J. Carlos, Hernandez, C., and Abella, J., Towards Certification-aware Fault Injection Methodologies Using Virtual Prototypes, 10th IEEE Forum on specification & Design Languages (FDL), Barcelona, Spain. 2015.
C. Hernandez, Abella, J., Cazorla, F., Andersson, J., and Gianarro, A., Towards Making a LEON3 Multicore Compatible with Probabilistic Timing Analysis, 20th Data Systems In Aerospace Conference (DASIA), Barcelona, Spain. 2015.
J. Abella, Hernandez, C., Quiñones, E., Cazorla, F., Conmy, P. Ryan, Azkarate-askasua, M., Perez, J., Mezzetti, E., and Vardanega, T., WCET Analysis Methods: Pitfalls and Challenges on their Trustworthiness, 10th IEEE International Symposium on Industrial Embedded Systems (SIES) Siegen, Germany. 2015.
2014
J. Jalle, Abella, J., Quiñones, E., Fossati, L., Zulianello, M., and Cazorla, F., AHRB: A High-Performance Time-Composable AMBA AHB Bus, 20th IEEE Real-Time and Embedded Technology and Applications Symposium. IEEE, Berlin, Germany, pp. 225–236, 2014.
B. Maric, Abella, J., and Valero, M., Analyzing the Efficiency of L1 Caches for Reliable Hybrid-Voltage Operation Using EDC Codes, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22. pp. 266-275, 2014.
J. Jalle, Kosmidis, L., Abella, J., Quiñones, E., and Cazorla, F., Bus designs for time-probabilistic multicore processors, Design, Automation and Test in Europe. Dresden, Germany, 2014.
J. Abella, Hardy, D., Puaut, I., Quiñones, E., and Cazorla, F., On the Comparison of Deterministic and Probabilistic WCET Estimation Techniques, 26th Euromicro Conference on Real-Time Systems. IEEE, Madrid, Spain, pp. 266–275, 2014.
L. Kosmidis, Abella, J., Quiñones, E., Wartel, F., Farrall, G., and Cazorla, F., Containing Timing-Related Certification Cost in Automotive Systems Deploying Complex Hardware, 51th Design Automation Conference (DAC) 2014. San Francisco, United States, pp. 1–6, 2014.
G. Fernandez, Abella, J., Quiñones, E., Rochange, C., Vardanega, T., and Cazorla, F., Contention in Multicore Hardware Shared Resources: Understanding of the State of the Art, 14th International Workshop on Worst-Case Execution Time Analysis. OASIcs, Madrid, Spain, pp. 31–42, 2014.
Q. Liu, Moreto, M., Abella, J., Cazorla, F., and Valero, M., DReAM: Per-Task DRAM Energy Metering in Multicore Systems, 20th International EUROPAR Conference. European Conference on Parallel and Distributed Computing. Springer, Porto, Portugal, pp. 111–123, 2014.
J. Jalle, Quiñones, E., Abella, J., Fossati, L., Zulianello, M., and Cazorla, F., A Dual-Criticality Memory Controller (DCmc): Proposal and Evaluation for a Space Case Study, 35th IEEE Real-Time Systems Symposium. IEEE, Rome, Italy, 2014.
L. Kosmidis, Abella, J., Quiñones, E., and Cazorla, F., Efficient Cache Designs for Probabilistically Analysable Real-Time Systems, IEEE Transactions on Computers, vol. 63. pp. 2998–3011, 2014.
J. Abella, Quiñones, E., Wartel, F., Vardanega, T., and Cazorla, F., Heart of Gold: Making the Improbable Happen to Increase Confidence in MBPTA, Real-Time Systems (ECRTS), 2014 26th Euromicro Conference on. pp. 255-265, 2014.
B. Maric, Abella, J., Cazorla, F., and Valero, M., Hybrid Cache Designs for Reliable Hybrid High and Ultra-Low Voltage Operation, ACM Transactions on Design Automation of Electronic Systems (ACM TODAES). 2014.
C. Hernandez and Abella, J., LiVe: Timely Error Detection in Light-Lockstep Safety Critical Systems, 51th Design Automation Conference (DAC) 2014. San Francisco, United States, pp. 1–6, 2014.
L. Kosmidis, Quiñones, E., Abella, J., Vardanega, T., Broster, I., and Cazorla, F., Measurement-Based Probabilistic Timing Analysis and Its Impact on Processor Architecture, 17th Euromicro Conference on Digital System Design. IEEE, Verona, Italy, pp. 401–410, 2014.
M. Panic, Quiñones, E., Zaykov, P., Hernandez, C., Abella, J., and Cazorla, F., Parallel Many-Core Avionics Systems, 14th International Conference on Embedded Software. ACM, New Delhi, India, 2014.
Q. Liu, Jiménez, V., Moreto, M., Abella, J., Cazorla, F., and Valero, M., Per-task Energy Accounting in Computing Systems, IEEE Computer Architecture Letters (IEEE CAL) . 2014.
L. Kosmidis, Abella, J., Wartel, F., Quiñones, E., Colin, A., and Cazorla, F., PUB: Path Upper-Bounding for Measurement-Based Probabilistic Timing Analysis, 26th Euromicro Conference on Real-Time Systems. IEEE, Madrid, Spain, pp. 276–287, 2014.
M. Panic, Kehr, S., Quiñones, E., Boeddeker, B., Abella, J., and Cazorla, F., RunPar: An Allocation Algorithm for Automotive Applications Exploiting Runnable Parallelism in Multicores, 12th International Conference on Hardware/Software Codesign and System Synthesis. ACM, New Delhi, India, 2014.
M. Slijepcevic, Kosmidis, L., Abella, J., Quiñones, E., and Cazorla, F., Time-Analysable Non-Partitioned Shared Caches for Real-Time Multicore Systems, 51th Design Automation Conference (DAC) 2014. San Francisco, United States, pp. 1–6, 2014.
M. Slijepcevic, Kosmidis, L., Abella, J., Quiñones, E., and Cazorla, F., Timing Verification of Fault-Tolerant Chips for Safety-Critical Applications in Harsh Environments, IEEE Micro, vol. 34. pp. 8–19, 2014.
2013
L. Kosmidis, Quiñones, E., Abella, J., Vardanega, T., and Cazorla, F., Achieving Timing Composability with Probabilistic Timing Analysis, In IEEE International Symposium on Object-component-service-oriented Real-time distributed computing (ISORC). 2013.
B. Maric, Abella, J., and Valero, M., APPLE: Adaptive Performance-Predictable Low-Energy Caches for Reliable Hybrid Voltage Operation, 50th Annual Design Automation Conference (DAC). ACM, Austin (Texas), United States, pp. 1–6, 2013.
L. Kosmidis, Abella, J., Quiñones, E., and Cazorla, F., A Cache Design for Probabilistically Analysable Real-Time Systems, ACM/IEEE Design, Automation, and Test in Europe (DATE). ACM, IEEE, Grenoble, France, pp. 513–518, 2013.
S. Girbal, Moretó, M., Grasset, A., Abella, J., Quiñones, E., Cazorla, F., and Yehia, S., On the Convergence of Mainstream and Mission Critical Markets, 50th Annual Design Automation Conference (DAC). ACM, Austin (Texas), United States, pp. 1–10, 2013.

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