Publications

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2013
Kosmidis, L., Quiñones, E., Abella, J., Vardanega, T. & Cazorla, F.J. Achieving Timing Composability with Probabilistic Timing Analysis. In IEEE International Symposium on Object-component-service-oriented Real-time distributed computing (ISORC) (2013).at <http://people.ac.upc.edu/equinone/docs/2013/isorc_2013.pdf>
Maric, B., Abella, J. & Valero, M. APPLE: Adaptive Performance-Predictable Low-Energy Caches for Reliable Hybrid Voltage Operation. 50th Annual Design Automation Conference (DAC) 1–6 (2013).
Kosmidis, L., Abella, J., Quiñones, E. & Cazorla, F.J. A Cache Design for Probabilistically Analysable Real-Time Systems. ACM/IEEE Design, Automation, and Test in Europe (DATE) 513–518 (2013).at <http://hpc.ac.upc.edu/PDFs/dir20/file004138.pdf>
Girbal, S., Moretó, M., Grasset, A., Abella, J., Quiñones, E., Cazorla, F.J. & Yehia, S. On the Convergence of Mainstream and Mission Critical Markets. 50th Annual Design Automation Conference (DAC) 1–10 (2013).doi:10.1145/2463209.2488962
Jalle, J., Abella, J., Quiñones, E., Fossati, L., Zulianello, M. & Cazorla, F.J. Deconstructing Bus Access Control Policies for Real-Time Multicores. 8th IEEE International Symposium on Industrial Embedded Systems (SIES) 31–38 (2013).doi:10.1109/SIES.2013.6601468
Slijepcevic, M., Kosmidis, L., Abella, J., Quiñones, E. & Cazorla, F.J. DTM: Degraded Test Mode for Fault-Aware Probabilistic Timing Analysis. 25th Euromicro Conference on Real-Time Systems (ECRTS13) (2013).doi:10.1109/ECRTS.2013.33
Maric, B., Abella, J. & Valero, M. Efficient Cache Architectures for Reliable Hybrid Voltage Operation Using EDC Codes. Proceedings of the Conference on Design, Automation and Test in Europe 917–920 (2013).at <http://dl.acm.org/citation.cfm?id=2485288.2485508>
Liu, Q., Moreto, M., Jimenez, V., Abella, J., Cazorla, F.J. & Valero, M. Hardware Support for Accurate Per-task Energy Metering in Multicore Systems. ACM Trans. Archit. Code Optim. 10, 34:1–34:27 (2013).
Sazeides, Y., Ozer, E., Kershaw, D., Nikolaou, P., Kleanthous, M. & Abella, J. Implicit-Storing and Redundant-Encoding-of-Attribute Information in Error-Correction-Codes. 46th IEEE/ACM International Symposium on Microarchitecture (MICRO) 160–171 (2013).doi:10.1145/2540708.2540723
Wartel, F., Kosmidis, L., Lo, C., Triquet, B., Quiñones, E., Abella, J., Gogonel, A., Baldovin, A., Mezzetti, E., Cucu-Grosjean, L., Vardanega, T. & Cazorla, F.J. Measurement-Based Probabilistic Timing Analysis: Lessons from an Integrated-Modular Avionics Case Study. 8th IEEE International Symposium on Industrial Embedded Systems (SIES) (2013).doi:10.1109/SIES.2013.6601497
Kosmidis, L., Vardanega, T., Quiñones, E., Abella, J. & Cazorla, F.J. Measurement-Based Probabilistic Timing Analysis to Buffer Resources. 13th International Workshop on Worst-Case Execution Time Analysis 2–10 (2013).
Kosmidis, L., Abella, J., Quiñones, E. & Cazorla, F.J. Multi-Level Unified Caches for Probabilistically Time Analysable Real-Time Systems. IEEE Real-Time Systems Symposium (RTSS) 2013 (2013).
Girbal, S., Moretó, M., Grasset, A., Abella, J., Quiñones, E., Cazorla, F.J. & Yehia, S. The Next Convergence: High-performance and Mission-critical Markets. Workshop on High-performance and Real-time Embedded Systems (HiRES) 1–11 (2013).
Panic, M., Rodríguez, G., Quiñones, E., Abella, J. & Cazorla, F.J. On-Chip Ring Network Designs for Hard-Real Time Systems. 21st International Conference on Real-Time Networks and Systems 23–32 (2013).doi:10.1145/2516821.2516829
Ungerer, T., Bradatsch, C., Gerdes, M., Kluge, F., Jahr, R., Mische, J., Fernandes, J., Zaykov, P., Zlatko, P., Boddeker, B., Kehr, S., Regler, H., Hugl, A., Rochange, C., Ozaktas, H., Cassé, H., Armelle, B., Sainrat, P., Lay, N., Broster, I., George, D., Panic, M., Quiñones, E., Cazorla, F.J., Abella, J., Uhrig, S., Rohde, M. & Pyka, A. parMERASA Multi-Core Execution of Parallelised Hard Real-Time Applications Supporting Analysability. Euromicro Conference on Digital System Design, DSD 2013 363–370 (2013).doi: 10.1109/DSD.2013.46
Liu, Q., Jimenez, V., Moreto, M., Abella, J., Francisco, & Cazorla, F.J. Per-task Energy Accounting in Computing Systems. In IEEE Computer Architecture Letters (CAL) (2013).doi:http://people.ac.upc.edu/jabella/camerareadyIEEECAL.pdf‎
Cazorla, F.J., Quiñones, E., Vardanega, T., Cucu, L., Triquet, B., Bernat, G., Berger, E., Abella, J., Wartel, F., Houston, M., Santinelli, L., Kosmidis, L., Lo, C. & Maxim, D. PROARTIS: Probabilistically Analyzable Real-Time Systems. ACM Trans. Embed. Comput. Syst. 12, 94:1–94:26 (2013).
Kosmidis, L., Curtsinger, C., Quiñones, E., Abella, J., Berger, E.D. & Cazorla, F.J. Probabilistic Timing Analysis on Conventional Cache Designs. ACM/IEEE Design, Automation, and Test in Europe (DATE) 603–606 (2013).at <http://hpc.ac.upc.edu/PDFs/dir21/file004139.pdf>
Stephenson, Z., Abella, J. & Vardanega, T. Supporting Industrial Use of Probabilistic Timing Analysis with Explicit Argumentation. 11th IEEE International Conference on Industrial Informatics (INDIN) 734–740 (2013).doi:10.1109/INDIN.2013.6622975
Cazorla, F.J., Vardanega, T., Quiñones, E. & Abella, J. Upper-bounding Program Execution Time with Extreme Value Theory. 13th International Workshop on Worst-Case Execution Time Analysis 61–70 (2013).
2011
Quiñones, E., Abella, J., Cazorla, F. & Valero, M. Exploiting Intra-Task Slack Time of Load Operations for DVFS in Hard Real-Time Multi-core Systems. In Work in Progess (WiP), under the the 24nd Euromicro Conference on Real-Time Systems (ECRTS 2011) (2011).
Maric, B., Abella, J., Cazorla, F. & Valero, M. Hybrid High-Performance Low-Power and Ultra-Low Energy Reliable Caches. International Conference on Computing Frontiers (CF) 12:1-12:2 (2011).
Liu, Q., Moretó, M., Abella, J. & Cazorla, F. Online Performance Prediction in Processors with DVFS Capabilities. ACACES 2011. Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems (2011).
Abella, J., Quiñones, E., Cazorla, F., Sazeides, Y. & Valero, M. RVC: A Mechanism for Time-Analyzable Real-Time Processors with Faulty Caches. (2011).at <http://www.hipeac.net/conference>
Abella, J., Quiñones, E., Cazorla, F., Valero, M. & Sazeides, Y. RVC-based time-predictable faulty caches for safety-critical systems. IOLTS 25-30 (2011).at <http://dblp.uni-trier.de/db/conf/iolts/iolts2011.html#AbellaQCVS11>
Abella, J., Cazorla, F., Quiñones, E., Grasset, A., Yehia, S., Bonnot, P., Gizopoulos, D., Mariani, R. & Bernat, G. Towards improved survivability in safety-critical systems. International On-Line Testing Symposium (IOLTS) 240-245 (2011).