Publications

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2014
J. Jalle, Abella, J., Quiñones, E., Fossati, L., Zulianello, M., and Cazorla, F. J., AHRB: A High-Performance Time-Composable AMBA AHB Bus, in 20th IEEE Real-Time and Embedded Technology and Applications Symposium, Berlin, Germany, 2014, pp. 225–236.
B. Maric, Abella, J., and Valero, M., Analyzing the Efficiency of L1 Caches for Reliable Hybrid-Voltage Operation Using EDC Codes, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 22, no. 10. pp. 2211 - 2215, 2014.
B. Maric, Abella, J., and Valero, M., Analyzing the Efficiency of L1 Caches for Reliable Hybrid-Voltage Operation Using EDC Codes, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22. pp. 2211–2215, 2014.
B. Maric, Abella, J., and Valero, M., Analyzing the Efficiency of L1 Caches for Reliable Hybrid-Voltage Operation Using EDC Codes, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22. pp. 2211–2215, 2014.
J. Jalle, Kosmidis, L., Abella, J., Quiñones, E., and Cazorla, F. J., Bus designs for time-probabilistic multicore processors, in Design, Automation and Test in Europe, Dresden, Germany, 2014.
J. Jalle, Kosmidis, L., Abella, J., Quiñones, E., and Cazorla, F. J., Bus Designs for Time-probabilistic Multicore Processors, Proceedings of the Conference on Design, Automation & Test in Europe. European Design and Automation Association, 3001 Leuven, Belgium, Belgium, pp. 50:1–50:6, 2014.
J. Abella, Hardy, D., Puaut, I., Quiñones, E., and Cazorla, F. J., On the Comparison of Deterministic and Probabilistic WCET Estimation Techniques, Real-Time Systems (ECRTS), 2014 26th Euromicro Conference on. pp. 266-275, 2014.
J. Abella, Hardy, D., Puaut, I., Quiñones, E., and Cazorla, F. J., On the Comparison of Deterministic and Probabilistic WCET Estimation Techniques, in 26th Euromicro Conference on Real-Time Systems, Madrid, Spain, 2014, pp. 266–275.
L. Kosmidis, Abella, J., Quiñones, E., Wartel, F., Farrall, G., and Cazorla, F. J., Containing Timing-Related Certification Cost in Automotive Systems Deploying Complex Hardware, in 51th Design Automation Conference (DAC) 2014, San Francisco, United States, 2014, pp. 1–6.
L. Kosmidis, Quiñones, E., Abella, J., Farrall, G., Wartel, F., and Cazorla, F. J., Containing Timing-Related Certification Cost in Automotive Systems Deploying Complex Hardware, Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference. ACM, New York, NY, USA, pp. 22:1–22:6, 2014.
G. Fernandez, Abella, J., Quiñones, E., Rochange, C., Vardanega, T., and Cazorla, F. J., Contention in Multicore Hardware Shared Resources: Understanding of the State of the Art, 14th International Workshop on Worst-Case Execution Time Analysis, vol. 39. Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik, Dagstuhl, Germany, pp. 31–42, 2014.
G. Fernandez, Abella, J., Quiñones, E., Rochange, C., Vardanega, T., and Cazorla, F. J., Contention in Multicore Hardware Shared Resources: Understanding of the State of the Art, in 14th International Workshop on Worst-Case Execution Time Analysis, Madrid, Spain, 2014, pp. 31–42.
Q. Liu, Moreto, M., Abella, J., Cazorla, F. J., and Valero, M., DReAM: Per-Task DRAM Energy Metering in Multicore Systems, 20th International EUROPAR Conference. European Conference on Parallel and Distributed Computing. Springer, Porto, Portugal, pp. 111–123, 2014.
J. Jalle, Quiñones, E., Abella, J., Fossati, L., Zulianello, M., and Cazorla, F. J., A Dual-Criticality Memory Controller (DCmc): Proposal and Evaluation for a Space Case Study, in 35th IEEE Real-Time Systems Symposium, Rome, Italy, 2014.
L. Kosmidis, Abella, J., Quiñones, E., and Cazorla, F. J., Efficient Cache Designs for Probabilistically Analysable Real-Time Systems, IEEE Transactions on Computers, vol. 63. pp. 2998–3011, 2014.
L. Kosmidis, Abella, J., Quiñones, E., and Cazorla, F. J., Efficient Cache Designs for Probabilistically Analysable Real-Time Systems, IEEE Transactions on Computers, vol. 63. pp. 2998–3011, 2014.
J. Abella, Quiñones, E., Wartel, F., Vardanega, T., and Cazorla, F. J., Heart of Gold: Making the Improbable Happen to Extend Coverage in Probabilistic Timing Analysis, in 26th Euromicro Conference on Real-Time Systems, Madrid, Spain, 2014, pp. 255–265.
J. Abella, Quiñones, E., Wartel, F., Vardanega, T., and Cazorla, F. J., Heart of Gold: Making the Improbable Happen to Increase Confidence in MBPTA, Real-Time Systems (ECRTS), 2014 26th Euromicro Conference on. pp. 255-265, 2014.
B. Maric, Abella, J., Cazorla, F. J., and Valero, M., Hybrid Cache Designs for Reliable Hybrid High and Ultra Low Voltage Operation, ACM Transactions on Design Automation of Electronic Systems, vol. 20. 2014.
B. Maric, Abella, J., Cazorla, F. J., and Valero, M., Hybrid Cache Designs for Reliable Hybrid High and Ultra-Low Voltage Operation, ACM Transactions on Design Automation of Electronic Systems, vol. 20. 2014.
C. Hernandez and Abella, J., LiVe: Timely Error Detection in Light-Lockstep Safety Critical Systems, in 51th Design Automation Conference (DAC) 2014, San Francisco, United States, 2014, pp. 1–6.
C. Hernandez and Abella, J., LiVe: Timely Error Detection in Light-Lockstep Safety Critical Systems, Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference. ACM, New York, NY, USA, pp. 25:1–25:6, 2014.
L. Kosmidis, Quiñones, E., Abella, J., Vardanega, T., Broster, I., and Cazorla, F. J., Measurement-Based Probabilistic Timing Analysis and Its Impact on Processor Architecture, in 17th Euromicro Conference on Digital System Design, Verona, Italy, 2014, pp. 401–410.
L. Kosmidis, Quiñones, E., Abella, J., Vardanega, T., Broster, I., and Cazorla, F. J., Measurement-Based Probabilistic Timing Analysis and Its Impact on Processor Architecture, Digital System Design (DSD), 2014 17th Euromicro Conference on. pp. 401-410, 2014.
M. Panic, Quiñones, E., Zaykov, P., Hernandez, C., Abella, J., and Cazorla, F. J., Parallel Many-Core Avionics Systems, in 14th International Conference on Embedded Software, New Delhi, India, 2014.
M. Panic, Quiñones, E., Zaykov, P., Hernandez, C., Abella, J., and Cazorla, F. J., Parallel Many-core Avionics Systems, Proceedings of the 14th International Conference on Embedded Software. ACM, New York, NY, USA, pp. 26:1–26:10, 2014.
Q. Liu, Jiménez, V., Moreto, M., Abella, J., Cazorla, F. J., and Valero, M., Per-task Energy Accounting in Computing Systems, IEEE Computer Architecture Letters, vol. 13. pp. 85–88, 2014.
L. Kosmidis, Abella, J., Wartel, F., Quiñones, E., Colin, A., and Cazorla, F. J., PUB: Path Upper-Bounding for Measurement-Based Probabilistic Timing Analysis, Real-Time Systems (ECRTS), 2014 26th Euromicro Conference on. pp. 276-287, 2014.
L. Kosmidis, Abella, J., Wartel, F., Quiñones, E., Colin, A., and Cazorla, F. J., PUB: Path Upper-Bounding for Measurement-Based Probabilistic Timing Analysis, in 26th Euromicro Conference on Real-Time Systems, Madrid, Spain, 2014, pp. 276–287.
M. Panic, Kehr, S., Quiñones, E., Boeddeker, B., Abella, J., and Cazorla, F. J., RunPar: An Allocation Algorithm for Automotive Applications Exploiting Runnable Parallelism in Multicores, in 12th International Conference on Hardware/Software Codesign and System Synthesis, New Delhi, India, 2014.
M. Panic, Kehr, S., Quiñones, E., Boddecker, B., Abella, J., and Cazorla, F. J., RunPar: An Allocation Algorithm for Automotive Applications Exploiting Runnable Parallelism in Multicores, Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis. ACM, New York, NY, USA, pp. 29:1–29:10, 2014.
M. Slijepcevic, Kosmidis, L., Abella, J., Quiñones, E., and Cazorla, F. J., Time-Analysable Non-Partitioned Shared Caches for Real-Time Multicore Systems, Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference. ACM, New York, NY, USA, pp. 198:1–198:6, 2014.
M. Slijepcevic, Kosmidis, L., Abella, J., Quiñones, E., and Cazorla, F. J., Time-Analysable Non-Partitioned Shared Caches for Real-Time Multicore Systems, in 51th Design Automation Conference (DAC) 2014, San Francisco, United States, 2014, pp. 1–6.
M. Slijepcevic, Kosmidis, L., Abella, J., Quiñones, E., and Cazorla, F. J., Timing Verification of Fault-Tolerant Chips for Safety-Critical Applications in Harsh Environments, Micro, IEEE, vol. 34. pp. 1-12, 2014.
M. Slijepcevic, Kosmidis, L., Abella, J., Quiñones, E., and Cazorla, F. J., Timing Verification of Fault-Tolerant Chips for Safety-Critical Applications in Harsh Environments, IEEE Micro, vol. 34. pp. 8–19, 2014.
M. Slijepcevic, Kosmidis, L., Abella, J., Quiñones, E., and Cazorla, F. J., Timing Verification of Fault-Tolerant Chips for Safety-Critical Applications in Harsh Environments, IEEE Micro, vol. 34. pp. 8–19, 2014.
2013
L. Kosmidis, Quiñones, E., Abella, J., Vardanega, T., and Cazorla, F. J., Achieving Timing Composability with Probabilistic Timing Analysis, In IEEE International Symposium on Object-component-service-oriented Real-time distributed computing (ISORC). 2013.
B. Maric, Abella, J., and Valero, M., APPLE: Adaptive Performance-Predictable Low-Energy Caches for Reliable Hybrid Voltage Operation, 50th Annual Design Automation Conference (DAC). ACM, Austin (Texas), United States, pp. 1–6, 2013.
L. Kosmidis, Abella, J., Quiñones, E., and Cazorla, F. J., A Cache Design for Probabilistically Analysable Real-Time Systems, ACM/IEEE Design, Automation, and Test in Europe (DATE). ACM, IEEE, Grenoble, France, pp. 513–518, 2013.
S. Girbal, Moretó, M., Grasset, A., Abella, J., Quiñones, E., Cazorla, F. J., and Yehia, S., On the Convergence of Mainstream and Mission Critical Markets, 50th Annual Design Automation Conference (DAC). ACM, Austin (Texas), United States, pp. 1–10, 2013.
J. Jalle, Abella, J., Quiñones, E., Fossati, L., Zulianello, M., and Cazorla, F. J., Deconstructing Bus Access Control Policies for Real-Time Multicores, 8th IEEE International Symposium on Industrial Embedded Systems (SIES). IEEE, Porto, Portugal, pp. 31–38, 2013.
M. Slijepcevic, Kosmidis, L., Abella, J., Quiñones, E., and Cazorla, F. J., DTM: Degraded Test Mode for Fault-Aware Probabilistic Timing Analysis, 25th Euromicro Conference on Real-Time Systems (ECRTS13). 00, Paris, France, 2013.
B. Maric, Abella, J., and Valero, M., Efficient Cache Architectures for Reliable Hybrid Voltage Operation Using EDC Codes, Proceedings of the Conference on Design, Automation and Test in Europe. EDA Consortium, San Jose, CA, USA, pp. 917–920, 2013.
L. Kosmidis, Abella, J., Quiñones, E., and Cazorla, F., Efficient Cache Designs for Probabilistically Analysable Real-time Systems, Computers, IEEE Transactions on, vol. PP. pp. 1-1, 2013.
Q. Liu, Moreto, M., Jiménez, V., Abella, J., Cazorla, F. J., and Valero, M., Hardware Support for Accurate Per-task Energy Metering in Multicore Systems, ACM Trans. Archit. Code Optim., vol. 10. ACM, New York, NY, USA, pp. 34:1–34:27, 2013.
Y. Sazeides, Ozer, E., Kershaw, D., Nikolaou, P., Kleanthous, M., and Abella, J., Implicit-Storing and Redundant-Encoding-of-Attribute Information in Error-Correction-Codes, 46th IEEE/ACM International Symposium on Microarchitecture (MICRO). ACM, Davis (California), United States, pp. 160–171, 2013.

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