Publications

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2016
J. Jalle, Fernández, M., Abella, J., Andersson, J., Patte, M., Fossati, L., Zulianello, M., and Cazorla, F., Bounding Resource-Contention Interference in the Next-Generation Multipurpose Processor (NGMP), 8th European Congress on Embedded Real Time Software and Systems (ERTS^2). 2016.
P. Benedicte, Kosmidis, L., Quiñones, E., Abella, J., and Cazorla, F., A Confidence Assessment of WCET Estimates for Software Time Randomized Caches, 14th International Conference on Industrial Informatics (INDIN). IEEE, 2016.
J. Jalle, Fernández, M., Abella, J., Andersson, J., Patte, M., Fossati, L., Zulianello, M., and Cazorla, F., Contention-Aware Performance Monitoring Counter Support for Real-Time MPSoCs, 11th IEEE International Symposium on Industrial Embedded Systems (SIES). 2016.
J. Jalle, Quiñones, E., Abella, J., Fossati, L., Zulianello, M., and Cazorla, F., Data Bus Slicing for Contention-Free Multicore Real-Time Memory Systems, 11th IEEE International Symposium on Industrial Embedded Systems (SIES). 2016.
M. Riera, Canal, R., Abella, J., and González, A., A Detailed Methodology to Compute Soft Error Rates in Advanced Technologies, In Proceedings of the Design Automation and Test in Europe (DATE) Dresden, Germany. 2016.
D. Trilla, Jalle, J., Fernández, M., Abella, J., and Cazorla, F. J., Improving Early Design Stage Timing Modeling in Multicore Based Real-Time Systems, IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), Vienna, Austria, April 11-14, 2016. pp. 305–316, 2016.
F. Cazorla, Abella, J., Andersson, J., Vardanega, T., Vatrinet, F., Bate, I., Broster, I., Azkarate-askasua, M., Wartel, F., Cucu-Grosjean, L., Cros, F., Farrall, G., Gogonel, A., Gianarro, A., Triquet, B., Hernandez, C., Lo, C., Maxim, C., Morales, D., Quiñones, E., Mezzetti, E., Kosmidis, L., Agirre, I., Fernández, M., Slijepcevic, M., Conmy, P. Ryan, and Talaboulma, W., Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis, 19th Euromicro Conference on Digital Systems Design (DSD). 2016.
M. Panic, Hernandez, C., Abella, J., Roca, A., Quiñones, E., and Cazorla, F. J., Improving performance guarantees in wormhole mesh NoC designs, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, March 14-18, 2016. pp. 1485–1488, 2016.
L. Kosmidis, Compagnin, D., Morales, D., Mezzetti, E., Quiñones, E., Abella, J., Vardanega, T., and Cazorla, F., Measurement-Based Timing Analysis of the AURIX Caches, 16th International Workshop on Worst-Case Execution Time Analysis (WCET). 2016.
E. Díaz, Abella, J., Mezzetti, E., Agirre, I., Azkarate-askasua, M., Vardanega, T., and Cazorla, F., Mitigating Software-Instrumentation Cache Effects in Measurement-Based Timing Analysis, 16th International Workshop on Worst-Case Execution Time Analysis (WCET). 2016.
M. Panic, Hernandez, C., Quiñones, E., Abella, J., and Cazorla, F., Modeling High-Performance Wormhole NoCs for Critical Real-Time Embeddedd Systems, 22nd IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), Viena, Austria. 2016.
J. Espinosa, Hernandez, C., and Abella, J., Modeling RTL Fault Models Behavior to Increase the Confidence on TSIM-based Fault Injection, 22nd IEEE International On-Line Testing Symposium (IOLTS). 2016.
S. Milutinovic, Abella, J., and Cazorla, F., Modelling Probabilistic Cache Representativeness in the Presence of Arbitrary Access Patterns, ISORC 2016 19th IEEE Symposium On Real-Time Computing . 2016.
P. Benedicte, Kosmidis, L., Quiñones, E., Abella, J., and Cazorla, F., Modelling the Confidence of Timing Analysis for Time Randomised Caches, 11th IEEE International Symposium on Industrial Embedded Systems (SIES). IEEE, 2016.
T. Ungerer, Bradatsch, C., Frieb, M., Kluge, F., Mische, J., Stegmeier, A., Jahr, R., Gerdes, M., Zaykov, P., Matusova, L., Li, Z. Jian Jia, Petrov, Z., Böddeker, B., Kehr, S., Regler, H., Hugl, A., Rochange, C., Ozaktas, H., Cassé, H., Bonenfant, A., Sainrat, P., Lay, N., George, D., Broster, I., Quiñones, E., Panic, M., Abella, J., Hernandez, C., Cazorla, F., Uhrig, S., Rohde, M., and Pyka, A., Parallelizing Industrial Hard Real-Time Applications for the parMERASA Multicore, ACM Trans. Embed. Comput. Syst., vol. 15. ACM, New York, NY, USA, pp. 53:1–53:27, 2016.
M. Slijepcevic, Fernández, M., Hernandez, C., Abella, J., Quiñones, E., and Cazorla, F., pTNoC: Probabilistically Time-Analyzable Tree-Based NoC for Mixed-Criticality Systems, 19th Euromicro Conference on Digital Systems Design (DSD). 2016.
C. Hernandez, Abella, J., Gianarro, A., Andersson, J., and Cazorla, F., Random Modulo: a New Processor Cache Design for Real-Time Critical Systems, 53rd Design Automation Conference (DAC). 2016.
D. Trilla, Hernandez, C., Abella, J., and Cazorla, F., Resilient Random Modulo Cache Memories for Probabilistically-Analyzable Real-Time Systems, 22nd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS). IEEE, 2016.
Q. Liu, Moreto, M., Abella, J., Cazorla, F., Jiménez, D. A., and Valero, M., Sensible Energy Accounting with Abstract Metering for Multicore Systems, ACM Transactions on Architecture and Code Optimization (TACO), vol. 12, no. 11th International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC). 2016.
S. Kehr, Panic, M., Quiñones, E., Boddeker, B., Sandoval, J. Becerril, Abella, J., Cazorla, F. J., and Schäfer, G., Supertask: Maximizing runnable-level parallelism in AUTOSAR applications, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) , Dresden, Germany, March 14-18, 2016. pp. 25–30, 2016.
L. Kosmidis, Vargas, R., Morales, D., Quiñones, E., Abella, J., and Cazorla, F., TASA: Toolchain-Agnostic Static Software Randomisation for Critical Real-Time Systems, 35th International Conference On Computer Aided Design (ICCAD). 2016.
J. Jalle, Abella, J., Fossati, L., Zulianello, M., and Cazorla, F., Validating a Timing Simulator for the NGMP Multicore Processor, 21st Data Systems In Aerospace Conference (DASIA). 2016.
2015
J. Espinosa, Hernandez, C., Abella, J., De Andres, D., and Ruiz, J. Carlos, Analysis and RTL Correlation of Instruction Set Simulators for Automotive Microcontroller Robustness Verification, Design Automation Conference (DAC), 2015 52nd ACM/EDAC/IEEE. 2015.
M. Panic, Quiñones, E., Hernandez, C., Abella, J., and Cazorla, F., CAP: Communication-aware Allocation Algorithm for Real-Time Parallel Applications on Many-cores, 18th Euromicro Conference on Digital System Design (DSD) Madeira, Portugal. 2015.
J. Espinosa, Hernandez, C., and Abella, J., Characterizing Fault Propagation in Safety-Critical Processor Designs, 21st IEEE International On-Line Testing Symposium (IOLTS), Elia, Halkidiki, Greece. pp. 144-149, 2015.
M. Panic, Abella, J., Hernandez, C., Quiñones, E., Ungerer, T., and Cazorla, F., Enabling TDMA Arbitration in the Context of MBPTA, 18th Euromicro Conference on Digital System Design (DSD) Madeira, Portugal. 2015.
M. Ziccardi, Mezzetti, E., Vardanega, T., Abella, J., and Cazorla, F., EPC: Extended Path Coverage for Measurement-based Probabilistic Timing Analysis, IEEE Real-Time Systems Symposium (RTSS) San Antonio, Texas. pp. 338-349, 2015.
T. Ungerer, Bradatsch, C., Frieb, M., Kluge, F., Mische, J., Stegmeier, A., Jahr, R., Gerdes, M., Zaykov, P., Matusova, L., Li, Z. Jian Jia, Petrov, Z., Boddeker, B., Kehr, S., Regler, H., Hugl, A., Roc, C., Ozaktas, H., Casse, H., Bonenfant, A., Sainrat, P., Lay, N., George, D., Broster, I., Quiñones, E., Panic, M., Abella, J., Hernandez, C., Cazorla, F., Uhrig, S., Rohde, M., and Pyka, A., Experiences and Results of Parallelisation of Industrial Hard Real-time Applications for the parMERASA Multi-core, 3rd Workshop on High-performance and Real-time Embedded Systems (HiRES), Amsterdam, The Netherlands. 2015.
J. Abella, del Castillo, J., Cazorla, F., and Padilla, M., Extreme value theory in computer sciences: The case of embedded safety-critical systems, 6th International Conference on Risk Analysis (ICRA). 2015.
I. Agirre, Azkarate-askasua, M., Perez, J., Hernandez, C., Abella, J., Vardanega, T., and Cazorla, F., IEC-61508 SIL 3-compliant Pseudo-Random Number Generators for Probabilistic Timing Analysis, 18th Euromicro Conference on Digital System Design (DSD) Madeira, Portugal. pp. 677-684, 2015.
G. Fernandez, Jalle, J., Abella, J., Quiñones, E., Vardanega, T., and Cazorla, F., Increasing Confidence on Measurement-Based Contention Bounds for Real-Time Round-Robin Buses, Design Automation Conference (DAC) San Francisco, CA. 2015.
G. Fernandez, Abella, J., Quiñones, E., Fossati, L., Zulianello, M., Vardanega, T., and Cazorla, F., Introduction to Partial Time Composability for COTS Multicores, SAC '15 Proceedings of the 30th Annual ACM Symposium on Applied Computing . pp. 1955-1956, 2015.
C. Hernandez and Abella, J., Low-cost Checkpointing in Automotive Safety-Relevant Systems, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE) . pp. 91-96, 2015.
S. Milutinovic, Quiñones, E., Abella, J., and Cazorla, F., PACO: Fast Average-Performance Estimation for Time-Randomized Caches, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC) . pp. 1-6, 2015.
E. Mezzetti, Ziccardi, M., Vardanega, T., Abella, J., Quiñones, E., and Cazorla, F., Randomized Caches Can Be Pretty Useful to Hard Real-Time Systems, LITES, vol. 2, no. 1. 2015.
G. Fernandez, Jalle, J., Abella, J., Quiñones, E., Vardanega, T., and Cazorla, F., Resource Usage Templates and Signatures for COTS Multicore Processors, DAC '15 Proceedings of the 52nd Annual Design Automation Conference . pp. 1-6, 2015.
G. Fernandez, Abella, J., Quiñones, E., Fossati, L., Zulianello, M., Vardanega, T., and Cazorla, F., Seeking Time-Composable Partitions of Tasks for COTS Multicore Processors, IEEE 18th International Symposium on Real-Time Distributed Computing, (ISORC). pp. 208-217, 2015.
S. Milutinovic, Abella, J., Hardy, D., Quiñones, E., Puaut, I., and Cazorla, F., Speeding up Static Probabilistic Timing Analysis, Architecture of Computing Systems – ARCS 2015, vol. 9017, no. Lecture Notes in Computer Science. pp. 236-247, 2015.
C. Hernandez and Abella, J., Timely Error Detection for Effective Recovery in Light-Lockstep Automotive Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 34, no. 11. pp. 1718-1729, 2015.
F. Wartel, Kosmidis, L., Gogonel, A., Baldovin, A., Stephenson, Z., Triquet, B., Quiñones, E., Lo, C., Mezzetti, E., Broster, I., Abella, J., Cucu-Grosjean, L., Vardanega, T., and Cazorla, F., Timing Analysis of an Avionics Case Study on Complex Hardware/Software Platforms, DATE '15 Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition. pp. 397-402, 2015.
J. Espinosa, De Andres, D., Ruiz, J. Carlos, Hernandez, C., and Abella, J., Towards Certification-aware Fault Injection Methodologies Using Virtual Prototypes, 10th IEEE Forum on specification & Design Languages (FDL), Barcelona, Spain. 2015.
C. Hernandez, Abella, J., Cazorla, F., Andersson, J., and Gianarro, A., Towards Making a LEON3 Multicore Compatible with Probabilistic Timing Analysis, 20th Data Systems In Aerospace Conference (DASIA), Barcelona, Spain. 2015.
J. Abella, Hernandez, C., Quiñones, E., Cazorla, F., Conmy, P. Ryan, Azkarate-askasua, M., Perez, J., Mezzetti, E., and Vardanega, T., WCET Analysis Methods: Pitfalls and Challenges on their Trustworthiness, 10th IEEE International Symposium on Industrial Embedded Systems (SIES) . pp. 1-10, 2015.
2014
J. Jalle, Abella, J., Quiñones, E., Fossati, L., Zulianello, M., and Cazorla, F., AHRB: A High-Performance Time-Composable AMBA AHB Bus, 20th IEEE Real-Time and Embedded Technology and Applications Symposium. IEEE, Berlin, Germany, pp. 225–236, 2014.
B. Maric, Abella, J., and Valero, M., Analyzing the Efficiency of L1 Caches for Reliable Hybrid-Voltage Operation Using EDC Codes, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22. pp. 266-275, 2014.
J. Jalle, Kosmidis, L., Abella, J., Quiñones, E., and Cazorla, F., Bus designs for time-probabilistic multicore processors, Design, Automation and Test in Europe. Dresden, Germany, 2014.
J. Abella, Hardy, D., Puaut, I., Quiñones, E., and Cazorla, F., On the Comparison of Deterministic and Probabilistic WCET Estimation Techniques, 26th Euromicro Conference on Real-Time Systems. IEEE, Madrid, Spain, pp. 266–275, 2014.
L. Kosmidis, Abella, J., Quiñones, E., Wartel, F., Farrall, G., and Cazorla, F., Containing Timing-Related Certification Cost in Automotive Systems Deploying Complex Hardware, 51th Design Automation Conference (DAC) 2014. San Francisco, United States, pp. 1–6, 2014.
G. Fernandez, Abella, J., Quiñones, E., Rochange, C., Vardanega, T., and Cazorla, F., Contention in Multicore Hardware Shared Resources: Understanding of the State of the Art, 14th International Workshop on Worst-Case Execution Time Analysis. OASIcs, Madrid, Spain, pp. 31–42, 2014.
Q. Liu, Moreto, M., Abella, J., Cazorla, F., and Valero, M., DReAM: Per-Task DRAM Energy Metering in Multicore Systems, 20th International EUROPAR Conference. European Conference on Parallel and Distributed Computing. Springer, Porto, Portugal, pp. 111–123, 2014.

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