Publications

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2014
Jalle, J. et al. AHRB: A High-Performance Time-Composable AMBA AHB Bus. 20th IEEE Real-Time and Embedded Technology and Applications Symposium (2014).
Maric, B., Abella, J. & Valero, M. Analyzing the Efficiency of L1 Caches for Reliable Hybrid-Voltage Operation Using EDC Codes. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 22, 2211 - 2215 (2014).
Jalle, J., Kosmidis, L., Abella, J., Quiñones, E. & Cazorla, F. J. Bus Designs for Time-probabilistic Multicore Processors. Proceedings of the Conference on Design, Automation & Test in Europe 50:1–50:6 (2014). at <http://dl.acm.org/citation.cfm?id=2616606.2616668>
Abella, J., Hardy, D., Puaut, I., Quiñones, E. & Cazorla, F. J. On the Comparison of Deterministic and Probabilistic WCET Estimation Techniques. Real-Time Systems (ECRTS), 2014 26th Euromicro Conference on 266-275 (2014). doi:10.1109/ECRTS.2014.16
Kosmidis, L. et al. Containing Timing-Related Certification Cost in Automotive Systems Deploying Complex Hardware. Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference 22:1–22:6 (2014). doi:10.1145/2593069.2593112
Fernandez, G. et al. Contention in Multicore Hardware Shared Resources: Understanding of the State of the Art. 14th International Workshop on Worst-Case Execution Time Analysis 39, 31–42 (2014).
Liu, Q., Moreto, M., Abella, J., Cazorla, F. J. & Valero, M. DReAM: Per-Task DRAM Energy Metering in Multicore Systems. Euro-Par 2014 Parallel Processing - 20th International Conference, Porto, Portugal, August 25-29, 2014. Proceedings 111–123 (2014). doi:10.1007/978-3-319-09873-9_10
Jalle, J. et al. A Dual-Criticality Memory Controller (DCmc): Proposal and Evaluation for a Space Case Study. 35th IEEE Real-Time Systems Symposium (2014).
Abella, J., Quiñones, E., Wartel, F., Vardanega, T. & Cazorla, F. J. Heart of Gold: Making the Improbable Happen to Increase Confidence in MBPTA. Real-Time Systems (ECRTS), 2014 26th Euromicro Conference on 255-265 (2014). doi:10.1109/ECRTS.2014.33
Hernandez, C. & Abella, J. LiVe: Timely Error Detection in Light-Lockstep Safety Critical Systems. Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference 25:1–25:6 (2014). doi:10.1145/2593069.2593155
Kosmidis, L. et al. Measurement-Based Probabilistic Timing Analysis and Its Impact on Processor Architecture. Digital System Design (DSD), 2014 17th Euromicro Conference on 401-410 (2014). doi:10.1109/DSD.2014.50
Panic, M. et al. Parallel Many-core Avionics Systems. Proceedings of the 14th International Conference on Embedded Software 26:1–26:10 (2014). doi:10.1145/2656045.2656063
Kosmidis, L. et al. PUB: Path Upper-Bounding for Measurement-Based Probabilistic Timing Analysis. Real-Time Systems (ECRTS), 2014 26th Euromicro Conference on 276-287 (2014). doi:10.1109/ECRTS.2014.34
Panic, M. et al. RunPar: An Allocation Algorithm for Automotive Applications Exploiting Runnable Parallelism in Multicores. Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis 29:1–29:10 (2014). doi:10.1145/2656075.2656096
Slijepcevic, M., Kosmidis, L., Abella, J., Quiñones, E. & Cazorla, F. J. Time-Analysable Non-Partitioned Shared Caches for Real-Time Multicore Systems. Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference 198:1–198:6 (2014). doi:10.1145/2593069.2593235
Slijepcevic, M., Kosmidis, L., Abella, J., Quiñones, E. & Cazorla, F. J. Timing Verification of Fault-Tolerant Chips for Safety-Critical Applications in Harsh Environments. Micro, IEEE 34, 1-12 (2014).
2013
Kosmidis, L., Quiñones, E., Abella, J., Vardanega, T. & Cazorla, F. J. Achieving Timing Composability with Probabilistic Timing Analysis. In IEEE International Symposium on Object-component-service-oriented Real-time distributed computing (ISORC) (2013). at <http://people.ac.upc.edu/equinone/docs/2013/isorc_2013.pdf>
Maric, B., Abella, J. & Valero, M. APPLE: Adaptive Performance-Predictable Low-Energy Caches for Reliable Hybrid Voltage Operation. 50th Annual Design Automation Conference (DAC) 1–6 (2013).
Kosmidis, L., Abella, J., Quiñones, E. & Cazorla, F. J. A Cache Design for Probabilistically Analysable Real-Time Systems. ACM/IEEE Design, Automation, and Test in Europe (DATE) 513–518 (2013). at <http://hpc.ac.upc.edu/PDFs/dir20/file004138.pdf>
Girbal, S. et al. On the Convergence of Mainstream and Mission Critical Markets. 50th Annual Design Automation Conference (DAC) 1–10 (2013). doi:10.1145/2463209.2488962
Jalle, J. et al. Deconstructing Bus Access Control Policies for Real-Time Multicores. 8th IEEE International Symposium on Industrial Embedded Systems (SIES) 31–38 (2013). doi:10.1109/SIES.2013.6601468
Slijepcevic, M., Kosmidis, L., Abella, J., Quiñones, E. & Cazorla, F. J. DTM: Degraded Test Mode for Fault-Aware Probabilistic Timing Analysis. 25th Euromicro Conference on Real-Time Systems (ECRTS13) (2013). doi:10.1109/ECRTS.2013.33
Maric, B., Abella, J. & Valero, M. Efficient Cache Architectures for Reliable Hybrid Voltage Operation Using EDC Codes. Proceedings of the Conference on Design, Automation and Test in Europe 917–920 (2013). at <http://dl.acm.org/citation.cfm?id=2485288.2485508>
Kosmidis, L., Abella, J., Quiñones, E. & Cazorla, F. Efficient Cache Designs for Probabilistically Analysable Real-time Systems. Computers, IEEE Transactions on PP, 1-1 (2013).
Liu, Q. et al. Hardware Support for Accurate Per-task Energy Metering in Multicore Systems. ACM Trans. Archit. Code Optim. 10, 34:1–34:27 (2013).
Sazeides, Y. et al. Implicit-Storing and Redundant-Encoding-of-Attribute Information in Error-Correction-Codes. 46th IEEE/ACM International Symposium on Microarchitecture (MICRO) 160–171 (2013). doi:10.1145/2540708.2540723
Wartel, F. et al. Measurement-Based Probabilistic Timing Analysis: Lessons from an Integrated-Modular Avionics Case Study. 8th IEEE International Symposium on Industrial Embedded Systems (SIES) (2013). doi:10.1109/SIES.2013.6601497
Kosmidis, L., Vardanega, T., Quiñones, E., Abella, J. & Cazorla, F. J. Measurement-Based Probabilistic Timing Analysis to Buffer Resources. 13th International Workshop on Worst-Case Execution Time Analysis 2–10 (2013).
Kosmidis, L., Abella, J., Quiñones, E. & Cazorla, F. J. Multi-Level Unified Caches for Probabilistically Time Analysable Real-Time Systems. IEEE Real-Time Systems Symposium (RTSS) 2013 (2013).
Girbal, S. et al. The Next Convergence: High-performance and Mission-critical Markets. Workshop on High-performance and Real-time Embedded Systems (HiRES) 1–11 (2013).
Panic, M., Rodríguez, G., Quiñones, E., Abella, J. & Cazorla, F. J. On-Chip Ring Network Designs for Hard-Real Time Systems. 21st International Conference on Real-Time Networks and Systems 23–32 (2013). doi:10.1145/2516821.2516829
Ungerer, T. et al. parMERASA Multi-Core Execution of Parallelised Hard Real-Time Applications Supporting Analysability. Euromicro Conference on Digital System Design, DSD 2013 363–370 (2013). doi: 10.1109/DSD.2013.46
Liu, Q. et al. Per-task Energy Accounting in Computing Systems. In IEEE Computer Architecture Letters (CAL) (2013). doi:http://people.ac.upc.edu/jabella/camerareadyIEEECAL.pdf‎
Cazorla, F. J. et al. PROARTIS: Probabilistically Analyzable Real-Time Systems. ACM Trans. Embed. Comput. Syst. 12, 94:1–94:26 (2013).
Kosmidis, L. et al. Probabilistic Timing Analysis on Conventional Cache Designs. ACM/IEEE Design, Automation, and Test in Europe (DATE) 603–606 (2013). at <http://hpc.ac.upc.edu/PDFs/dir21/file004139.pdf>
Stephenson, Z., Abella, J. & Vardanega, T. Supporting Industrial Use of Probabilistic Timing Analysis with Explicit Argumentation. 11th IEEE International Conference on Industrial Informatics (INDIN) 734–740 (2013). doi:10.1109/INDIN.2013.6622975
Cazorla, F. J., Vardanega, T., Quiñones, E. & Abella, J. Upper-bounding Program Execution Time with Extreme Value Theory. 13th International Workshop on Worst-Case Execution Time Analysis 61–70 (2013).