Publications

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Filters: Author is Adrián Cristal  [Clear All Filters]
1996
A. Cristal, Síntesis de Redes de Petri. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 1996.
1997
A. Cristal, Un simulador de un procesador similar al MIPS R10000. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 1997.
2002
A. Cristal, Valero, M., González, A., and Llosa, J., Large Virtual ROBs by Processor Checkpointing. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2002.
A. Cristal and Valero, M., ROBs Virtuales utilizando checkpoints, XIII Jornadas de Paralelismo. Edicions de la Universitat de Lleida, Lleida, Spain, 2002.
2003
R. González, Cristal, A., Ortega, D., and Valero, M., Arquitecturas Basadas en el Contenido, XIV Jornadas de Paralelismo. Leganés, Spain, pp. 541–546, 2003.
A. Cristal, Martínez, J. F., Llosa, J., and Valero, M., A Case for Resource Conscious Out-of-Order Processor, MEDEA Workshop MEmory performance: DEaling with Applications , systems and architecture (MEDEA 2003). New Orleans, LA, United States, 2003.
A. Cristal, Martínez, J. F., Llosa, J., and Valero, M., A Case for Resource-conscious Out-of-order Processors. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2003.
A. Cristal, Martínez, J. F., Llosa, J., and Valero, M., A Case for Resource-conscious Out-of-order Processors, Computer Architecture Letters, vol. 2, 2003.
R. González, Cristal, A., Ortega, D., and Valero, M., Content Aware Register File Organisation. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2003.
A. Cristal, Martínez, J. F., Llosa, J., and Valero, M., Ephemeral Registers with Multicheckpointing. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2003.
A. Cristal, Ortega, D., Llosa, J., and Valero, M., Kilo-instruction Processors, 5th International Symposium on High Performance Computing (ISHPC-V). Springer-Verlag, Tokio, Japan, pp. 10–25, 2003.
M. A. Ramírez, Cristal, A., Veidenbaum, A., Villa, L. A., and Valero, M., A Low-Power-Instruction-Queue Wakeup Mechanism, XIV Jornadas de Paralelismo. Leganés, Spain, pp. 533–540, 2003.
A. Cristal, Martínez, J. F., Llosa, J., and Valero, M., Optimal Use of Registers in Aggressive Superscalar Processors, XIV Jornadas de Paralelismo. Leganés, Spain, pp. 553–558, 2003.
A. Cristal, Martínez, J. F., Ortega, D., Llosa, J., and Valero, M., Out-of-Order Commit Processors. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2003.
M. A. Ramírez, Cristal, A., Veidenbaum, A., Villa, L. A., and Valero, M., A Simple Low-Energy Instruction Wakeup Mechanism, 5th International Symposium on High Performance Computing (ISHPC-V). Springer-Verlag, Tokio, Japan, pp. 99–112, 2003.
2004
M. Pericàs, González, R., Cristal, A., Veidenbaum, A., and Valero, M., Banked Front-End Register File. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2004.
A. Cristal, Martínez, J. F., Llosa, J., and Valero, M., A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors, ACM SIGARCH Computer Architecture News, vol. 32, pp. 3–10, 2004.
R. González, Cristal, A., Veidenbaum, A., Pericàs, M., and Valero, M., A clustered Processor based on Content-Aware Register File. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2004.
A. Cristal, Santana, O. J., and Valero, M., A Comprehensive Description of Kilo-Instruction Processors, 5o Congreso Nacional de Computación. Instituto Politécnico Nacional - Centro de Investigación en Computación, Mexico City, Mexico, pp. 144–154, 2004.
R. González, Cristal, A., Ortega, D., Veidenbaum, A., and Valero, M., A Content Aware Integer Register File Organization, International Symposium on Computer Architecture (ISCA 2004). IEEE/ACM Press, München, Germany, pp. 314–324, 2004.
M. A. Ramírez, Cristal, A., Villa, L. A., Veidenbaum, A., and Valero, M., Direct Instruction Wakeup for OOO processors, Innovative Architecture for Future Generation High-Performance Processors and System. IEEE Computer Society Press, Maui, Hawaii, United States, 2004.
M. Galluzzi, Puente, V., Cristal, A., Beivide, R., Monasterio, J. A. G., and Valero, M., Evaluating Kilo-instruction Multiprocessors, 3rd Workshop on Memory Performance Issues (WMPI-2004). ACM Press, München, Germany, pp. 72–79, 2004.
M. Galluzzi, Puente, V., Cristal, A., Beivide, R., Monasterio, J. A. G., and Valero, M., A first glance at Kilo-instruction based multiprocessors, International Conference on Computing Frontiers 2004 (CF'04). ACM Press, Ischia, Italy, pp. 212–221, 2004.
A. Cristal, Llosa, J., Valero, M., and Ortega, D., Future ILP processors, International Journal of High Performance Computing and Networking, vol. 2, pp. 1–10, 2004.
M. A. Ramírez, Cristal, A., Villa, L. A., Veidenbaum, A., and Valero, M., INSTRUCTION WAKEUP MECHANISM: Power and Timing Evaluation, in CIC,s Research and Computing Science, 2004.
M. Galluzzi, Puente, V., Santana, O. J., Acosta, C., Cristal, A., Beivide, R., Monasterio, J. A. G., and Valero, M., Introducing Kilo-instruction Multiprocessors, XV Jornadas de Paralelismo. Universidad de Almería, Servicio de Publicaciones, Almería, Spain, 2004.
A. Cristal, Santana, O. J., and Valero, M., Maintaining Thousands of In-Flight Instructions, 10th International Euro-Par 2004 Conference. Springer-Verlag, Pisa, Italy, pp. 9–20, 2004.
M. Pericàs, González, R., Cristal, A., Veidenbaum, A., and Valero, M., An Optimized Front-End Physical Register File with Banking and Writeback Filtering, Workshop on Power-Aware Computer Systems (PACS'04). Portland, OR, United States, pp. 4–13, 2004.
A. Cristal, Ortega, D., Llosa, J., and Valero, M., Out-of-Order Commit Processors, 10th International Symposium on High Performance Computer Architecture (HPCA-10). IEEE Computer Society Press, Madrid, Spain, pp. 48–59, 2004.
M. A. Ramírez, Cristal, A., Valero, M., Veidenbaum, A., and Villa, L. A., A partitioned instruction queue to reduce instruction wakeup energy, International Journal of High Performance Computing and Networking, vol. 1, pp. 153–161, 2004.
R. González, Cristal, A., Pericàs, M., Veidenbaum, A., and Valero, M., Scalable Distributed Register File, 5th Workshop on Complexity-Effective Design. München, Germany, pp. 5–14, 2004.
A. Cristal, Santana, O. J., Valero, M., and Martínez, J. F., Toward Kilo-instruction Processors, ACM Transactions on Architecture and Code Optimization, vol. 1, pp. 368–396, 2004.
2005
R. González, Cristal, A., Pericàs, M., Veidenbaum, A., and Valero, M., Arquitectura Simétrica Clusterizada basada en el Contenido, XVI Jornadas de Paralelismo. Thomson, Granada, Spain, 2005.
R. González, Cristal, A., Pericàs, M., Valero, M., and Veidenbaum, A., An asymetric Clustered Processor Based on Value Content, The 19th ACM International Conference on Supercomputing (ICS'05). ACM Press, Boston, MA, United States, pp. 61–70, 2005.
M. Pericàs, Cristal, A., González, R., and Valero, M., Decoupled State-Execute Architecture, 6th International Symposium on High Performance Computing (ISHPC-VI 2005). Springer-Verlag, Nara, Japan, pp. 68–78, 2005.
T. Ramírez, Galluzzi, M., Cristal, A., and Valero, M., Different approaches using Kilo-instruction Processors, 2005 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-2005). Academia Press, L'Aquila, Italy, 2005.
T. Ramírez, Cristal, A., Pajuelo, A., Santana, O. J., and Valero, M., Eficacia vs. Eficiencia: Una decisión de diseño en Runahead, XVI Jornadas de Paralelismo. Thomson, Granada, Spain, 2005.
M. Pericàs, Cristal, A., González, R., Jiménez, D. A., and Valero, M., Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor, 6th International Symposium on High Performance Computing (ISHPC-VI 2005). Springer-Verlag, Nara, Japan, pp. 56–67, 2005.
E. Vallejo, Galluzzi, M., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J. E., and Valero, M., Implementing Kilo-Instruction Multiprocessors, International Conference on Pervasive Services (ICPS 2005). IEEE, Santorini, Greece, pp. 325–336, 2005.
A. Cristal, Santana, O. J., Cazorla, F., Galluzzi, M., Ramírez, T., Pericàs, M., and Valero, M., Kilo-instruction Processors: Overcoming the Memory Wall, IEEE Micro, vol. 25. pp. 48–57, 2005.
E. Vallejo, Galluzzi, M., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J. E., and Valero, M., KIMP: Multicheckpointing Multiprocessors, XVI Jornadas de Paralelismo. Thomson, Granada, Spain, 2005.
M. A. Ramírez, Cristal, A., Valero, M., Veidenbaum, A., and Villa, L. A., A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation, IEEE International Conference on Computer Design (ICCD-2005). IEEE Computer Society Press, San José, CA, United States, pp. 647–653, 2005.
M. Pericàs, González, R., Cristal, A., and Valero, M., Overcoming the Memor Wall with D-KIPs, 2005 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-2005). Academia Press, L'Aquila, Italy, pp. 99–102, 2005.
A. García, Medina, P., Fernández, E., Santana, O. J., Cristal, A., and Valero, M., Towards the Loop Processor Architecture, XVI Jornadas de Paralelismo. Thomson, Granada, Spain, 2005.
2006
M. Pericàs, Cristal, A., González, R., Cazorla, F., Jiménez, D. A., and Valero, M., Boosting ILP{&}TLP with the Flexible Multi-Core (FMC), 2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06). Academia Press, L'Aquila, Italy, pp. 125–128, 2006.
E. Vallejo, Galluzzi, M., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J. E., and Valero, M., Chip Multiprocessors with Implicit Transactions, 2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06). Academia Press, L'Aquila, Italy, pp. 167–170, 2006.
M. Pericàs, Cristal, A., González, R., Jiménez, D., and Valero, M., A decoupled KILO-instruction processor, The 12th International Symposium on High-Performance Computer Architecture (HPCA-12). IEEE Press, Auctin, TX, United States, pp. 53–64, 2006.
A. Cristal, Kilo Instruction Processors, Universitat Politècnica de Catalunya (UPC), 2006.
T. Ramírez, Cristal, A., Santana, O. J., Pajuelo, A., and Valero, M., Kilo-Instruction Processors, RunAhead and Prefetch, ACM International Conference on Computing Frontiers (CF 2006). ACM Press, Ischia, Italy, 2006.
2007
M. Milovanovic, Unsal, O., Cristal, A., Stipić, S., Zyulkyarov, F., and Valero, M., Compile time support for using transactional memory in C/C++ applications, The 11th Annual Workshop on the Interaction between Compilers and Computer Architecture (INTERACT-11). Phoenix, AR, United States, pp. 16–23, 2007.

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