Publications

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1996
Cristal, A. Síntesis de Redes de Petri. (1996).
1997
Cristal, A. Un simulador de un procesador similar al MIPS R10000. (1997).
2002
Cristal, A., Valero, M., González, A. & Llosa, J. Large Virtual ROBs by Processor Checkpointing. (2002).at <http://capinfo.e.ac.upc.edu/PDFs/dir11/file000939.pdf>
Cristal, A. & Valero, M. ROBs Virtuales utilizando checkpoints. XIII Jornadas de Paralelismo (2002).
2003
González, R., Cristal, A., Ortega, D. & Valero, M. Arquitecturas Basadas en el Contenido. XIV Jornadas de Paralelismo 541–546 (2003).
Cristal, A., Martínez, J.F., Llosa, J. & Valero, M. A Case for Resource Conscious Out-of-Order Processor. MEDEA Workshop MEmory performance: DEaling with Applications , systems and architecture (MEDEA 2003) (2003).
Cristal, A., Martínez, J.F., Llosa, J. & Valero, M. A Case for Resource-conscious Out-of-order Processors. Computer Architecture Letters 2, (2003).
Cristal, A., Martínez, J.F., Llosa, J. & Valero, M. A Case for Resource-conscious Out-of-order Processors. (2003).
González, R., Cristal, A., Ortega, D. & Valero, M. Content Aware Register File Organisation. (2003).
Cristal, A., Martínez, J.F., Llosa, J. & Valero, M. Ephemeral Registers with Multicheckpointing. (2003).
Cristal, A., Ortega, D., Llosa, J. & Valero, M. Kilo-instruction Processors. 5th International Symposium on High Performance Computing (ISHPC-V) 10–25 (2003).
Ramírez, M.A., Cristal, A., Veidenbaum, A., Villa, L.A. & Valero, M. A Low-Power-Instruction-Queue Wakeup Mechanism. XIV Jornadas de Paralelismo 533–540 (2003).
Cristal, A., Martínez, J.F., Llosa, J. & Valero, M. Optimal Use of Registers in Aggressive Superscalar Processors. XIV Jornadas de Paralelismo 553–558 (2003).
Cristal, A., Martínez, J.F., Ortega, D., Llosa, J. & Valero, M. Out-of-Order Commit Processors. (2003).
Ramírez, M.A., Cristal, A., Veidenbaum, A., Villa, L.A. & Valero, M. A Simple Low-Energy Instruction Wakeup Mechanism. 5th International Symposium on High Performance Computing (ISHPC-V) 99–112 (2003).
2004
Pericàs, M., González, R., Cristal, A., Veidenbaum, A. & Valero, M. Banked Front-End Register File. (2004).
Cristal, A., Martínez, J.F., Llosa, J. & Valero, M. A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors. ACM SIGARCH Computer Architecture News 32, 3–10 (2004).
González, R., Cristal, A., Veidenbaum, A., Pericàs, M. & Valero, M. A clustered Processor based on Content-Aware Register File. (2004).
Cristal, A., Santana, O.J. & Valero, M. A Comprehensive Description of Kilo-Instruction Processors. 5o Congreso Nacional de Computación 144–154 (2004).
González, R., Cristal, A., Ortega, D., Veidenbaum, A. & Valero, M. A Content Aware Integer Register File Organization. International Symposium on Computer Architecture (ISCA 2004) 314–324 (2004).at <http://capinfo.e.ac.upc.edu/PDFs/dir23/file002981.pdf>
Ramírez, M.A., Cristal, A., Villa, L.A., Veidenbaum, A. & Valero, M. Direct Instruction Wakeup for OOO processors. Innovative Architecture for Future Generation High-Performance Processors and System (2004).
Galluzzi, M., Puente, V., Cristal, A., Beivide, R., Monasterio, J.A.G. & Valero, M. Evaluating Kilo-instruction Multiprocessors. 3rd Workshop on Memory Performance Issues (WMPI-2004) 72–79 (2004).at <http://capinfo.e.ac.upc.edu/PDFs/dir21/file002979.pdf>
Galluzzi, M., Puente, V., Cristal, A., Beivide, R., Monasterio, J.A.G. & Valero, M. A first glance at Kilo-instruction based multiprocessors. International Conference on Computing Frontiers 2004 (CF'04) 212–221 (2004).at <http://capinfo.e.ac.upc.edu/PDFs/dir20/file002978.pdf>
Cristal, A., Llosa, J., Valero, M. & Ortega, D. Future ILP processors. International Journal of High Performance Computing and Networking 2, 1–10 (2004).
Ramírez, M.A., Cristal, A., Villa, L.A., Veidenbaum, A. & Valero, M. INSTRUCTION WAKEUP MECHANISM: Power and Timing Evaluation. CIC,s Research and Computing Science (2004).
Galluzzi, M., Puente, V., Santana, O.J., Acosta, C., Cristal, A., Beivide, R., Monasterio, J.A.G. & Valero, M. Introducing Kilo-instruction Multiprocessors. XV Jornadas de Paralelismo (2004).at <http://capinfo.e.ac.upc.edu/PDFs/dir19/file002977.pdf>
Cristal, A., Santana, O.J. & Valero, M. Maintaining Thousands of In-Flight Instructions. 10th International Euro-Par 2004 Conference 9–20 (2004).
Pericàs, M., González, R., Cristal, A., Veidenbaum, A. & Valero, M. An Optimized Front-End Physical Register File with Banking and Writeback Filtering. Workshop on Power-Aware Computer Systems (PACS'04) 4–13 (2004).
Cristal, A., Ortega, D., Llosa, J. & Valero, M. Out-of-Order Commit Processors. 10th International Symposium on High Performance Computer Architecture (HPCA-10) 48–59 (2004).
Ramírez, M.A., Cristal, A., Valero, M., Veidenbaum, A. & Villa, L.A. A partitioned instruction queue to reduce instruction wakeup energy. International Journal of High Performance Computing and Networking 1, 153–161 (2004).
González, R., Cristal, A., Pericàs, M., Veidenbaum, A. & Valero, M. Scalable Distributed Register File. 5th Workshop on Complexity-Effective Design 5–14 (2004).
Cristal, A., Santana, O.J., Valero, M. & Martínez, J.F. Toward Kilo-instruction Processors. ACM Transactions on Architecture and Code Optimization 1, 368–396 (2004).
2005
González, R., Cristal, A., Pericàs, M., Veidenbaum, A. & Valero, M. Arquitectura Simétrica Clusterizada basada en el Contenido. XVI Jornadas de Paralelismo (2005).
González, R., Cristal, A., Pericàs, M., Valero, M. & Veidenbaum, A. An asymetric Clustered Processor Based on Value Content. The 19th ACM International Conference on Supercomputing (ICS'05) 61–70 (2005).at <http://capinfo.e.ac.upc.edu/PDFs/dir24/file003040.pdf>
Pericàs, M., Cristal, A., González, R. & Valero, M. Decoupled State-Execute Architecture. 6th International Symposium on High Performance Computing (ISHPC-VI 2005) 68–78 (2005).at <http://capinfo.e.ac.upc.edu/PDFs/dir15/file003263.pdf>
Ramírez, T., Galluzzi, M., Cristal, A. & Valero, M. Different approaches using Kilo-instruction Processors. 2005 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-2005) (2005).at <http://capinfo.e.ac.upc.edu/PDFs/dir02/file003076.pdf>
Ramírez, T., Cristal, A., Pajuelo, A., Santana, O.J. & Valero, M. Eficacia vs. Eficiencia: Una decisión de diseño en Runahead. XVI Jornadas de Paralelismo (2005).at <http://capinfo.e.ac.upc.edu/PDFs/dir01/file003075.pdf>
Pericàs, M., Cristal, A., González, R., Jiménez, D.A. & Valero, M. Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor. 6th International Symposium on High Performance Computing (ISHPC-VI 2005) 56–67 (2005).at <http://capinfo.e.ac.upc.edu/PDFs/dir16/file003264.pdf>
Vallejo, E., Galluzzi, M., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J.E. & Valero, M. Implementing Kilo-Instruction Multiprocessors. International Conference on Pervasive Services (ICPS 2005) 325–336 (2005).
Cristal, A., Santana, O.J., Cazorla, F., Galluzzi, M., Ramírez, T., Pericàs, M. & Valero, M. Kilo-instruction Processors: Overcoming the Memory Wall. IEEE Micro 25, 48–57 (2005).
Vallejo, E., Galluzzi, M., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J.E. & Valero, M. KIMP: Multicheckpointing Multiprocessors. XVI Jornadas de Paralelismo (2005).
Ramírez, M.A., Cristal, A., Valero, M., Veidenbaum, A. & Villa, L.A. A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation. IEEE International Conference on Computer Design (ICCD-2005) 647–653 (2005).
Pericàs, M., González, R., Cristal, A. & Valero, M. Overcoming the Memor Wall with D-KIPs. 2005 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-2005) 99–102 (2005).
García, A., Medina, P., Fernández, E., Santana, O.J., Cristal, A. & Valero, M. Towards the Loop Processor Architecture. XVI Jornadas de Paralelismo (2005).
2006
Pericàs, M., Cristal, A., González, R., Cazorla, F., Jiménez, D.A. & Valero, M. Boosting ILP{&}TLP with the Flexible Multi-Core (FMC). 2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06) 125–128 (2006).
Vallejo, E., Galluzzi, M., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J.E. & Valero, M. Chip Multiprocessors with Implicit Transactions. 2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06) 167–170 (2006).
Pericàs, M., Cristal, A., González, R., Jiménez, D. & Valero, M. A decoupled KILO-instruction processor. The 12th International Symposium on High-Performance Computer Architecture (HPCA-12) 53–64 (2006).at <http://capinfo.e.ac.upc.edu/PDFs/dir13/file003261.pdf>
Cristal, A. Kilo Instruction Processors. (2006).
Ramírez, T., Cristal, A., Santana, O.J., Pajuelo, A. & Valero, M. Kilo-Instruction Processors, RunAhead and Prefetch. ACM International Conference on Computing Frontiers (CF 2006) (2006).at <http://capinfo.e.ac.upc.edu/PDFs/dir05/file003137.pdf>
2007
Milovanovic, M., Unsal, O., Cristal, A., Stipić, S., Zyulkyarov, F. & Valero, M. Compile time support for using transactional memory in C/C++ applications. The 11th Annual Workshop on the Interaction between Compilers and Computer Architecture (INTERACT-11) 16–23 (2007).at <http://capinfo.e.ac.upc.edu/PDFs/dir10/file003751.pdf>

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