Publications

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Workshops
Miletić, N. et al. Transactification of a real-world system library. 5th ACM SIGPLAN Workshop on Transactional Computing - TRANSACT 2010 (2010).
Smiljkovic, V., Stipić, S., Unsal, O., Cristal, A. & Valero, M. Transaction Coalescing - Lowering Transactional Overheads by Merging Transactions. Sixth Workshop on Programmability Issues for Heterogeneous Multicores (MULTIPROG-2013) (2013).
Markovic, N. et al. Object Orienteed Execution Model (OOM). 2nd Workshop on New Directions in Computer Architecture (NDCA-2) Held in Conjunction with the 38th International Symposium on Computer Architecture (ISCA-38) (2011). at <http://ndca2.saclay.inria.fr/papers/markovic.pdf>
Markovic, N. et al. Object Oriented execution Model (OOM). New Directions in Computer Architecture (NDCA-2) (2011).
Kestor, G., Dalessandro, L., Cristal, A., Scott, M. L. & Unsal, O. Interchangeable Back Ends for STM Compilers. 6th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT) (2011).
Gajinov, V. et al. Integrating dataflow abstractions into transactional memory. Systems for Future Multi-Core Architectures (SFMA'11) (2011).
Gajinov, V. et al. Integrating Dataflow Abstractions into Transactional Memory. First Workshop on Systems for Future Multi-Core Architectures (SFMA'11) 1–6 (2011).
Kestor, G., Gioiosa, R., Unsal, O., Cristal, A. & Valero, M. Hardware/Software Techniques for Assisted Execution Runtime Systems. The 2nd Workshop on Runtime Environments, Systems, Layering and Virtualized Environments (RESoLVE) (2012).
Yalcin, G., Unsal, O., Cristal, A. & Valero, M. FaulTM-multi: Fault Tolerance for Multithreaded Applications Running on Transactional Memory Hardware. Workshop on Wild and Sane Ideas in Speculation and Transactions (2011).
Akpinar, E., Tomić, S., Cristal, A., Unsal, O. & Valero, M. A Comprehensive Study of Conflict Resolution Policies in Hardware Transactional Memory. 6th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT) (2011).
Miscellaneous
Sönmez, N., Cristal, A., Unsal, O., Harris, T. & Valero, M. Why you should profile Transactional Memory Applications on an Atomic Block basis: A Haskell Case Study. (2008).
Cristal, A. Un simulador de un procesador similar al MIPS R10000. (1997).
Hayes, T., Palomar, O., Unsal, O., Cristal, A. & Valero, M. True Vector Extensions for Decision Support DBMS Acceleration. (2011).
Cristal, A. Síntesis de Redes de Petri. (1996).
Armejach, A. et al. ShadowHTM: Using a dual-bitcell L1 Data Cache to Improve Hardware Transactional Memory Performance. (2010).
Cristal, A., Martínez, J. F., Ortega, D., Llosa, J. & Valero, M. Out-of-Order Commit Processors. (2003).
Cristal, A., Valero, M., González, A. & Llosa, J. Large Virtual ROBs by Processor Checkpointing. (2002). at <http://capinfo.e.ac.upc.edu/PDFs/dir11/file000939.pdf>
Cristal, A., Martínez, J. F., Llosa, J. & Valero, M. Ephemeral Registers with Multicheckpointing. (2003).
González, I. et al. A Distributed Processor State Management Architecture for Large-Window Processors. (2008).
González, R., Cristal, A., Ortega, D. & Valero, M. Content Aware Register File Organisation. (2003).
González, R., Cristal, A., Veidenbaum, A., Pericàs, M. & Valero, M. A clustered Processor based on Content-Aware Register File. (2004).
Cristal, A., Martínez, J. F., Llosa, J. & Valero, M. A Case for Resource-conscious Out-of-order Processors. (2003).
Pericàs, M., González, R., Cristal, A., Veidenbaum, A. & Valero, M. Banked Front-End Register File. (2004).
Markovic, N., González, R., Unsal, O., Valero, M. & Cristal, A. Architecture for Object-Oriented Programming Model. (2009). at <http://capinfo.e.ac.upc.edu/PDFs/dir11/file003491.pdf>
Journal Article
Kulkarni, C., Unsal, O., Cristal, A., Ayguadé, E. & Valero, M. Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions. ACM SIGPLAN Notices 44, 307–308 (2009).
Harris, T. et al. Transactional Memory: An Overview. IEEE Micro 27, 8–29 (2007).
Cristal, A., Santana, O. J., Valero, M. & Martínez, J. F. Toward Kilo-instruction Processors. ACM Transactions on Architecture and Code Optimization 1, 368–396 (2004).
Ramírez, M. A., Cristal, A., Valero, M., Veidenbaum, A. & Villa, L. A. A partitioned instruction queue to reduce instruction wakeup energy. International Journal of High Performance Computing and Networking 1, 153–161 (2004).
Milovanovic, M. et al. Nebelung: Execution Environment for Transactional OpenMP. International Journal of Parallel Programming 36, 326–346 (2008).
Cristal, A., Llosa, J., Valero, M. & Ortega, D. Future ILP processors. International Journal of High Performance Computing and Networking 2, 1–10 (2004).
Seyedi, A. et al. Circuit Design of a Dual-Versioning L1 Data Cache. Integration The VLSI Journal (2011).
Cristal, A., Martínez, J. F., Llosa, J. & Valero, M. A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors. ACM SIGARCH Computer Architecture News 32, 3–10 (2004).
Cristal, A., Martínez, J. F., Llosa, J. & Valero, M. A Case for Resource-conscious Out-of-order Processors. Computer Architecture Letters 2, (2003).
International Conferences
Hayes, T., Palomar, O., Unsal, O., Cristal, A. & Valero, M. Vector Extensions for Decision Support DBMS Acceleration. The 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO45) 166-176 (2012). doi:10.1109/MICRO.2012.24
Armejach, A. et al. Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory. Parallel Architectures and Compilation Techniques (PACT) 360–370 (2011).
Pericas, M. et al. A two-level Load/Store Queue based on Execution Locality. (2008).
Negi, A., Armejach, A., Cristal, A., Unsal, O. & Stenström, P. Transactional prefetching: narrowing the window of contention in hardware transactional memory. Parallel Architectures and Compilation Techniques (PACT) 181-190 (2012).
Sönmez, N. et al. TMbox: A Flexible and Reconfigurable 16-core Hybrid Transactional Memory System. The 19th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2011) 1–8 (2011).
Sonmez, N. et al. {TMbox}: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System. Proc. FCCM '11 146–153 (2011).
Sonmez, N. et al. TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System. Proc. FCCM '11 146–153 (2011).
Sonmez, N., Harris, T., Cristal, A., Unsal, O. & Valero, M. Taking the heat off transactions: Dynamic selection of pessimistic concurrency control. Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing 1–10 (2009). doi:10.1109/IPDPS.2009.5161032
Stipić, S. et al. TagTM - accelerating STMs with hardware tags for fast meta-data access. DATE 39-44 (2012).
Yalcin, G., Unsal, O., Cristal, A., Hur, I. & Valero, M. SymptomTM: Symptom Based Error Detection and Recovery Using Hardware Transactional Memory. Parallel Architectures and Compilation Techniques (PACT) 199–200 (2011).
Gajinov, V. et al. Supporting Stateful Tasks in a Dataflow Graph. Proceedings of the 21st international conference on Parallel architectures and compilation techniques 435–436 (2012).
Kestor, G. et al. STM2: A Parallel STM for High Performance Simultaneous Multi-Threading Systems. The 20th IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT) (2011).

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