Publications

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Workshops
N. Miletić, Smiljkovic, V., Perfumo, C., Harris, T., Cristal, A., Hur, I., Unsal, O., and Valero, M., Transactification of a real-world system library, 5th ACM SIGPLAN Workshop on Transactional Computing - TRANSACT 2010. Paris, France, 2010.
V. Smiljkovic, Stipić, S., Unsal, O., Cristal, A., and Valero, M., Transaction Coalescing - Lowering Transactional Overheads by Merging Transactions, Sixth Workshop on Programmability Issues for Heterogeneous Multicores (MULTIPROG-2013). Berlin, Germany, 2013.
N. Markovic, Nemirovsky, D., González, R., Ünsal, O. S., Valero, M., and Cristal, A., Object Orienteed Execution Model (OOM), 2nd Workshop on New Directions in Computer Architecture (NDCA-2) Held in Conjunction with the 38th International Symposium on Computer Architecture (ISCA-38). San Jose, California, Sunday June 5th, 2011.
N. Markovic, Nemirovsky, D., González, R., Unsal, O., Valero, M., and Cristal, A., Object Oriented execution Model (OOM), New Directions in Computer Architecture (NDCA-2). San Jose, California, United States, 2011.
G. Kestor, Dalessandro, L., Cristal, A., Scott, M. L., and Unsal, O., Interchangeable Back Ends for STM Compilers, 6th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT). San Jose Convention Center, United States, 2011.
V. Gajinov, Cristal, A., Milovanovic, M., Ayguadé, E., Unsal, O., and Valero, M., Integrating dataflow abstractions into transactional memory, Systems for Future Multi-Core Architectures (SFMA'11) . 2011.
V. Gajinov, Milovanovic, M., Unsal, O., Cristal, A., Ayguadé, E., and Valero, M., Integrating Dataflow Abstractions into Transactional Memory, First Workshop on Systems for Future Multi-Core Architectures (SFMA'11). Salzburg, Austria, pp. 1–6, 2011.
G. Kestor, Gioiosa, R., Unsal, O., Cristal, A., and Valero, M., Hardware/Software Techniques for Assisted Execution Runtime Systems, The 2nd Workshop on Runtime Environments, Systems, Layering and Virtualized Environments (RESoLVE). 2012.
G. Yalcin, Unsal, O., Cristal, A., and Valero, M., FaulTM-multi: Fault Tolerance for Multithreaded Applications Running on Transactional Memory Hardware, Workshop on Wild and Sane Ideas in Speculation and Transactions. Galveston Island, TX, United States, 2011.
E. Akpinar, Tomić, S., Cristal, A., Unsal, O., and Valero, M., A Comprehensive Study of Conflict Resolution Policies in Hardware Transactional Memory, 6th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT). San Jose Convention Center, United States, 2011.
PHD Thesis
A. Cristal, Kilo Instruction Processors, Universitat Politècnica de Catalunya (UPC), 2006.
National Conferences
O. Arcas, Sönmez, N., Unsal, O., Cristal, A., and Valero, M., A Flexible Hybrid Transactional Memory Multicore on FPGA, Jornadas de Paralelismo 2011. Servicio de Publicaciones. Universidad de La Laguna, Tenerife, 2011, La Laguna, Tenerife, Spain, pp. 283–289, 2011.
Miscellaneous
N. Sönmez, Cristal, A., Unsal, O., Harris, T., and Valero, M., Why you should profile Transactional Memory Applications on an Atomic Block basis: A Haskell Case Study. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, 2008.
A. Cristal, Un simulador de un procesador similar al MIPS R10000. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 1997.
T. Hayes, Palomar, O., Unsal, O., Cristal, A., and Valero, M., True Vector Extensions for Decision Support DBMS Acceleration. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, 2011.
A. Cristal, Síntesis de Redes de Petri. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 1996.
A. Armejach, Seyedi, A., Gil, R. T. J., Hur, I., Unsal, O., Cristal, A., and Valero, M., ShadowHTM: Using a dual-bitcell L1 Data Cache to Improve Hardware Transactional Memory Performance. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, 2010.
A. Cristal, Martínez, J. F., Ortega, D., Llosa, J., and Valero, M., Out-of-Order Commit Processors. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2003.
A. Cristal, Valero, M., González, A., and Llosa, J., Large Virtual ROBs by Processor Checkpointing. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2002.
A. Cristal, Martínez, J. F., Llosa, J., and Valero, M., Ephemeral Registers with Multicheckpointing. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2003.
I. González, Galluzzi, M., Veidenbaum, A., Ramírez, M. A., Cristal, A., and Valero, M., A Distributed Processor State Management Architecture for Large-Window Processors. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, 2008.
R. González, Cristal, A., Ortega, D., and Valero, M., Content Aware Register File Organisation. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2003.
R. González, Cristal, A., Veidenbaum, A., Pericàs, M., and Valero, M., A clustered Processor based on Content-Aware Register File. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2004.
A. Cristal, Martínez, J. F., Llosa, J., and Valero, M., A Case for Resource-conscious Out-of-order Processors. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2003.
M. Pericàs, González, R., Cristal, A., Veidenbaum, A., and Valero, M., Banked Front-End Register File. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2004.
N. Markovic, González, R., Unsal, O., Valero, M., and Cristal, A., Architecture for Object-Oriented Programming Model. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, 2009.
Journal Article
C. Kulkarni, Unsal, O., Cristal, A., Ayguadé, E., and Valero, M., Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions, ACM SIGPLAN Notices, vol. 44, pp. 307–308, 2009.
T. Harris, Cristal, A., Unsal, O., Ayguadé, E., Galiardi, F., Smith, B., and Valero, M., Transactional Memory: An Overview, IEEE Micro, vol. 27, pp. 8–29, 2007.
A. Cristal, Santana, O. J., Valero, M., and Martínez, J. F., Toward Kilo-instruction Processors, ACM Transactions on Architecture and Code Optimization, vol. 1, pp. 368–396, 2004.
M. A. Ramírez, Cristal, A., Valero, M., Veidenbaum, A., and Villa, L. A., A partitioned instruction queue to reduce instruction wakeup energy, International Journal of High Performance Computing and Networking, vol. 1, pp. 153–161, 2004.
M. Milovanovic, Ferrer, R., Gajinov, V., Unsal, O., Cristal, A., Ayguadé, E., and Valero, M., Nebelung: Execution Environment for Transactional OpenMP, International Journal of Parallel Programming, vol. 36, pp. 326–346, 2008.
A. Cristal, Llosa, J., Valero, M., and Ortega, D., Future ILP processors, International Journal of High Performance Computing and Networking, vol. 2, pp. 1–10, 2004.
A. Seyedi, Armejach, A., Cristal, A., Unsal, O., Hur, I., and Valero, M., Circuit Design of a Dual-Versioning L1 Data Cache, Integration The VLSI Journal, 2011.
A. Cristal, Martínez, J. F., Llosa, J., and Valero, M., A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors, ACM SIGARCH Computer Architecture News, vol. 32, pp. 3–10, 2004.
A. Cristal, Martínez, J. F., Llosa, J., and Valero, M., A Case for Resource-conscious Out-of-order Processors, Computer Architecture Letters, vol. 2, 2003.
Journal
P. Felber, Rivière, E., Moreira, W. M., Harmanci, D., Marlier, P., Diestelhorst, S., Hohmuth, M., Pohlack, M., Cristal, A., Hur, I., Unsal, O., Stenström, P., Dragojevic, A., Guerraoui, R., Kapalka, M., Gramoli, V., Drepper, U., Tomić, S., Afek, Y., Korland, G., Shavit, N., Fetzer, C., Nowack, M., and Riegel, T., The Velox Transactional Memory Stack, Micro, IEEE, vol. 30. pp. 76 -87, 2010.
S. Tomić, Cristal, A., Unsal, O., and Valero, M., Using Dynamic Runtime Testing for Rapid Development of Architectural Simulators, International Journal of Parallel Programming, vol. 42. pp. 119–139, 2014.
S. Tomić, Cristal, A., Unsal, O., and Valero, M., Using Dynamic Runtime Testing for Rapid Development of Architectural Simulators, International Journal of Parallel Programming. 2012.
S. Tomić, Cristal, A., Unsal, O., and Valero, M., Using Dynamic Runtime Testing for Rapid Development of Architectural Simulators, International Journal of Parallel Programming, vol. 42. pp. 119–139, 2014.
N. Markovic, Nemirovsky, D., Unsal, O., Valero, M., and Cristal, A., Thread Lock Section-aware Scheduling on Asymmetric Single-ISA Multi-Core, IEEE Computer Architecture Letters, vol. PP. pp. 1–4, 2014.
N. Markovic, Nemirovsky, D., Unsal, O., Valero, M., and Cristal, A., Thread Lock Section-aware Scheduling on Asymmetric Single-ISA Multi-Core, IEEE Computer Architecture Letters, vol. PP. pp. 1–4, 2014.
A. Cristal, Santana, O. J., Cazorla, F., Galluzzi, M., Ramírez, T., Pericàs, M., and Valero, M., Kilo-instruction Processors: Overcoming the Memory Wall, IEEE Micro, vol. 25. pp. 48–57, 2005.
G. Yalcin, Ergin, O., Islek, E., Unsal, O., and Cristal, A., Exploiting Existing Comparators for Fine-Grained Low-Cost Error Detection, ACM Transactions on Architecture and Code Optimization, vol. 11. pp. 32–32, 2014.
G. Yalcin, Ergin, O., Islek, E., Unsal, O., and Cristal, A., Exploiting Existing Comparators for Fine-Grained Low-Cost Error Detection, ACM Transactions on Architecture and Code Optimization, vol. 11. pp. 32–32, 2014.
S. Zafer Can, Yalcin, G., Ergin, O., Unsal, O., and Cristal, A., Bit Impact Factor: Towards making fair vulnerability comparison, Microprocessors and Microsystems, vol. 38. pp. 598–604, 2014.
S. Zafer Can, Yalcin, G., Ergin, O., Unsal, O., and Cristal, A., Bit Impact Factor: Towards making fair vulnerability comparison, Microprocessors and Microsystems, vol. 38. pp. 598–604, 2014.

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