Publications

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2012
Fernández, M., Gioiosa, R., Quiñones, E., Fossati, L., Zulianello, M. & Cazorla, F.J. Assessing the suitability of the NGMP multi-core processor in the Space domain. International Conference on Embedded Software (EMSOFT) (2012).
Manousopoulos, S., Moretó, M., Gioiosa, R., Koziris, N. & Cazorla, F.J. Characterizing Thread Placement in the IBM POWER7 Processor. IEEE International Symposium on Workload Characterization (IISWC-2013) 1–11 (2012).at <http://capinfo.e.ac.upc.edu/PDFs/dir07/file004125.pdf>
Luque, C., Moretó, M., Cazorla, F.J., Gioiosa, R., Buyuktosunoglu, A. & Valero, M. CPU Accounting for Multicore Processors. IEEE Transactions on Computers 61, 251–264 (2012).
Morari, A., Gioiosa, R., Wisniewski, R.W., Rosenburg, B., Inglett, T. & Valero, M. Evaluating the impact of tlb misses on future HPC systems. The 26th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2012) (2012).
Kestor, G., Gioiosa, R., Unsal, O., Cristal, A. & Valero, M. Hardware/Software Techniques for Assisted Execution Runtime Systems. The 2nd Workshop on Runtime Environments, Systems, Layering and Virtualized Environments (RESoLVE) (2012).
Jiménez, V., Gioiosa, R., Cazorla, F.J., Buyuktosunoglu, A., Bose, P. & O'Connell, F.P. Making Data Prefetch Smarter: Adaptive Prefetching on POWER7. 21st International Conference on Parallel Architectures and Compilation Techniques (PACT-2012) 137–146 (2012).
Morari, A., Boneti, C., Cazorla, F.J., Gioiosa, R., Cher, C.-Y., Buyuktosunoglu, A., Bose, P. & Valero, M. SMT Malleability in IBM POWER5 and POWER6 Processors. IEEE Transactions on Computers 00, (2012).
2011
Jimenez, V., Cazorla, F., Gioiosa, R., Kursun, E., Isci, C., Buyuktosunoglu, A., Bose, P. & Valero, M. A Case for Energy-Aware Accounting and Billing in Large-Scale Computing Facilities Cost Metrics and Design Implications. IEEE Micro (2011).
Jimenez, V., Cazorla, F., Gioiosa, R., Valero, M., Boneti, C., Kursun, E., Cher, C., Isci, C., Buyuktosunoglu, A. & Bose, P. Characterizing Power and Temperature Behavior of POWER6-Based System. (invited paper). IEEE Journal of Emerging and Selected Topics in Circuits and Systems (2011).
Morari, A., Gioiosa, R., Wisniewski, R., Cazorla, F. & Valero, M. A Quantitative Analysis of OS Noise. (2011).at <http://www.ipdps.org/>
Kestor, G., Gioiosa, R., Harris, T., Cristal, A., Unsal, O., Valero, M. & Hur, I. STM2: A Parallel STM for High Performance Simultaneous Multi-Threading Systems. The 20th IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT) (2011).
2010
Morari, A., Piermaria, F., Betti, E., Gioiosa, R. & Cesati, M. Analyzing OS noise for HPC systems. (2010).
Jiménez, V.J., Cazorla, F., Gioiosa, R., Kursun, E., Isci, C., Buyuktosunoglu, A. & Valero, M. A Case for Energy Aware Accounting in Large Scale Computing Facilities: Cost Metrics and Implications for Processor Design. (2010).
Gioiosa, R., McKee, S.A. & Valero, M. Designing OS for HPC Applications: Scheduling. (2010).
Luque, C., Moreto, M., Cazorla, F., Gioiosa, R. & Valero, M. ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs. (2010).
Paolieri, M., Bonesana, I., Gioiosa, R. & Valero, M. J-DSE: Joint Software and Hardware Design Space Exploration for Application Specific Processors. (2010).
Goel, B., McKee, S.A., Gioiosa, R., Singh, K., Bhadauria, M. & Cesati, M. Portable, Scalable, per-Core Power Estimation for Intelligent Resource Management. (2010).
Kedzierski, K., Cazorla, F., Gioiosa, R., Buyuktosunoglu, A. & Valero, M. Power and Performance Aware Reconfigurable Cache for CMPs. (2010).
Jiménez, V.J., Boneti, C., Cazorla, F., Gioiosa, R., Kursun, E., Cher, C.-Y., Isci, C., Buyuktosunoglu, A., Bose, P. & Valero, M. Power and Thermal Characterization of POWER6 System. (2010).
Gioiosa, R. Towards sustainable exascale computing. (2010).
Jiménez, V.J., Gioiosa, R., Kursun, E., Cazorla, F., Cher, C.-Y., Buyuktosunoglu, A., Bose, P. & Valero, M. Trends and techniques for energy efficient architectures. (2010).
Boneti, C., Gioiosa, R., Cazorla, F. & Valero, M. Using hardware resource allocation to balance HPC applications, Parallel and Distributed Computing. (2010).
2009
Luque, C., Moreto, M., Cazorla, F., Gioiosa, R., Buyuktosunoglu, A. & Valero, M. CPU accounting in CMP Processors. (2009).
Luque, C., Moreto, M., Cazorla, F., Gioiosa, R., Buyuktosunoglu, A. & Valero, M. ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs. (2009).
2008
Boneti, C., Cazorla, F., Gioiosa, R., Corbalán, J., Labarta, J. & Valero, M. Balancing HPC Applications Through Smart Allocation of Resources in MT Processors. (2008).at <http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4536293>
Boneti, C., Gioiosa, R., Cazorla, F. & Valero, M. A Dynamic Scheduler for Balancing HPC Applications. (2008).at <http://portal.acm.org/citation.cfm?id=1413412>
Radojkovic, P., Cakarevic, V., Verdú, J., Pajuelo, A., Gioiosa, R., Cazorla, F., Nemirovsky, M. & Valero, M. Measuring Operating System Overhead on CMT Processors. (2008).
Boneti, C., Cazorla, F., Gioiosa, R. & Valero, M. Scheduling Real-Time Systems With Explicit Resource Allocation Processors. (2008).
Boneti, C., Cazorla, F., Gioiosa, R., Cher, C.-Y., Buyuktosunoglu, A. & Valero, M. Software-Controlled Priority Characterization of POWER5 Processor. (2008).at <http://www2.computer.org/portal/web/csdl/doi/10.1109/ISCA.2008.8>
Cakarevic, V., Radojkovic, P., Verdú, J., Pajuelo, A., Gioiosa, R., Cazorla, F., Nemirovsky, M. & Valero, M. Understanding the overhead of the spin-lock loop in CMT architectures. (2008).