Publications

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2011
Isaza, S., Sánchez, F., Gaydadjiev, G.N., Ramirez, A. & Valero, M. Parameterizing Multicore Architectures for Multiple Sequence Alignment. 2011 International Conference on Computing Frontiers (2011).
Ciobanu, C., Martorell, X., Kuzmanov, G.K., Ramirez, A. & Gaydadjiev, G.N. Scalability Evaluation of a Polymorphic Register File: A CG Case Study. Architecture of Computing Systems - ARCS 2011 13-25 (2011).doi:10.1007/978-3-642-19137-4.
Isaza, S., Gaydadjiev, G.N., Sánchez, F. & Ramirez, A. Scaling HMMER Performance on Multicore Architectures. The Fifth International Conference on Complex, Intelligent, and Software Intensive Systems (CISIS-2011 (2011).
2010
Ramirez, A., Cabarcas, F., Juurlink, B., Mesa, M.A., Sánchez, F., Azevedo, A., Meenderinck, C., Ciobanu, C., Isaza, S. & Gaydadjiev, G.N. The SARC Architecture. IEEE Micro 30, 16-29 (2010).
Isaza, S., Sánchez, F., Gaydadjiev, G.N., Ramirez, A. & Valero, M. Scalability Analysis of Progressive Alignment in a Multicore. International Workshop on Multi-Core Computing Systems (MuCoCoS 2010) (2010).
Isaza, S., Sánchez, F., Gaydadjiev, G.N., Ramirez, A. & Valero, M. Scalability Analysis of Progressive Alignment on a Multicore. Fourth International Conference on Complex, Intelligent and Software Intensive Systems (CISIS '10) 889-894 (2010).at <http://dx.doi.org/10.1109/CISIS.2010.149>
2009
González, C., Jiménez-González, D., Martorell, X., Álvarez, C. & Gaydadjiev, G.N. Fast Evaluation Methodology for Automatic Custom Hardware Prototyping. (2009).at <http://bardd.ee.byu.edu/warp2009>
González, C., Jiménez, D.A., Martorell, X., Álvarez, C. & Gaydadjiev, G.N. Metodología para la generación y evaluación automática de hardware específico (in Spanish). (2009).
Cabrera, D., Martorell, X., Gaydadjiev, G.N., Ayguadé, E. & Jiménez-González, D. OpenMP Extensions for FPGA Accelerators. (2009).at <http://portal.acm.org/citation.cfm?id=1812714>
2008
Isaza, S., Sánchez, F., Gaydadjiev, G.N., Ramirez, A. & Valero, M. Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications. Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS'08) 53-64 (2008).
Pericas, M., Chaves, R., Gaydadjiev, G.N., Valero, M. & Vassiliadis, S. Vectorized AES Core for high-throughput secure environments. (2008).