Publications

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Cabarcas, F., Rico, A., Ródenas, D., Martorell, X., Ramirez, A. & Ayguadé, E. CellSim: A Cell Processor Simulation Infrastructure. 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07) 279-282 (2007).
Cabarcas, F., Rico, A., Ródenas, D., Martorell, X., Ramirez, A. & Ayguadé, E. CellSim: A Validated Modular Heterogeneous Multiprocessor Simulator. XVIII Jornadas de Paralelismo de Zaragoza 181-188 (2007).
Bellens, P., Pérez, J.M., Cabarcas, F., Ramirez, A., Badia, R.M. & Labarta, J. CellSs: Scheduling Techniques to Better Exploit Memory Hierarchy. (2009).
Vega, A., Rico, A., Cabarcas, F., Ramirez, A. & Valero, M. Comparing last-level cache designs for CMP architectures. IFMT '10: International Forum on Next-Generation Multicore/Manycore Technologies (2010).
D
Vujic, N., González, M., Ayguadé, E., Martorell, X., Ramirez, A. & Cabarcas, F. DMA++: On the Fly Data Realignment for On-Chip Memories. 16th IEEE International Symposium on High-Performance Computer Architecture (2010).
Vujic, N., Cabarcas, F., González, M., Ramirez, A., Martorell, X. & Ayguadé, E. DMA++: On the Fly Data Realignment for On-Chip Memories. Computers, IEEE Transactions on 61, 237 -250 (2012).
I
Rico, A., Cabarcas, F., Ródenas, D., Martorell, X., Ramirez, A. & Ayguadé, E. Implementation and Validation of a Cell Simulator using UNISIM. 3rd HiPEAC Industrial Workshop (2007).
Cabarcas, F., Rico, A., Etsion, Y. & Ramirez, A. Interleaving Granularity on High Bandwidth Memory Architecture for CMPs. Intl. Conf. on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS X) 250-257 (2010).at <http://dx.doi.org/10.1109/ICSAMOS.2010.5642060>
L
Sánchez, F., Cabarcas, F., Ramirez, A. & Valero, M. Long DNA Sequence Comparison on Multicore Architectures. 16th international Euro-Par conference on Parallel processing (2010).at <http://dx.doi.org/10.1007/978-3-642-15291-7_24>
M
Cabarcas, F., Rico, A., Ródenas, D., Martorell, X., Ramirez, A. & Ayguadé, E. A module based Cell processor simulator. 2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06) (2006).
S
Ramirez, A., Cabarcas, F., Juurlink, B., Mesa, M.A., Sánchez, F., Azevedo, A., Meenderinck, C., Ciobanu, C., Isaza, S. & Gaydadjiev, G.N. The SARC Architecture. IEEE Micro 30, 16-29 (2010).
Sánchez, F., Cabarcas, F., Ramirez, A. & Valero, M. Scalable multicore architectures for long DNA sequence comparison. Concurrency and Computation Practice and Experience 23, (2011).
Rico, A., Cabarcas, F., Villavieja, C., Pavlovic, M., Vega, A., Etsion, Y., Ramirez, A. & Valero, M. On the Simulation of Large-scale Architectures Using Multiple Application Abstraction Levels. ACM Transactions on Architecture and Code Optimization 8, 36 (2012).
T
Etsion, Y., Cabarcas, F., Rico, A., Ramirez, A., Badia, R.M., Ayguadé, E., Labarta, J. & Valero, M. Task Superscalar: An Out-of-Order Task Pipeline. IEEE/ACM Intl. Symp. on Microarchitecture (MICRO-43) 89-100 (2010).at <http://dx.doi.org/10.1109/MICRO.2010.13>
Rico, A., Duran, A., Cabarcas, F., Etsion, Y., Ramirez, A. & Valero, M. Trace-driven simulation of multithreaded applications. 2011 IEEE International Symposium on Performance Analysis of Systems and Software 87--96 (2011).