Export 15 results:
Sort by: Author Title Type [ Year (Desc)]
Filters: Author is Felipe Cabarcas  [Clear All Filters]
Sánchez, F., Cabarcas, F., Ramirez, A. & Valero, M. Scalable multicore architectures for long DNA sequence comparison. Concurrency and Computation Practice and Experience 23, (2011).
Rico, A., Duran, A., Cabarcas, F., Etsion, Y., Ramirez, A. & Valero, M. Trace-driven simulation of multithreaded applications. 2011 IEEE International Symposium on Performance Analysis of Systems and Software 87--96 (2011).
Vega, A., Rico, A., Cabarcas, F., Ramirez, A. & Valero, M. Comparing last-level cache designs for CMP architectures. IFMT '10: International Forum on Next-Generation Multicore/Manycore Technologies (2010).
Vujic, N., González, M., Ayguadé, E., Martorell, X., Ramirez, A. & Cabarcas, F. DMA++: On the Fly Data Realignment for On-Chip Memories. 16th IEEE International Symposium on High-Performance Computer Architecture (2010).
Cabarcas, F., Rico, A., Etsion, Y. & Ramirez, A. Interleaving Granularity on High Bandwidth Memory Architecture for CMPs. Intl. Conf. on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS X) 250-257 (2010).at <>
Sánchez, F., Cabarcas, F., Ramirez, A. & Valero, M. Long DNA Sequence Comparison on Multicore Architectures. 16th international Euro-Par conference on Parallel processing (2010).at <>
Ramirez, A., Cabarcas, F., Juurlink, B., Mesa, M.A., Sánchez, F., Azevedo, A., Meenderinck, C., Ciobanu, C., Isaza, S. & Gaydadjiev, G.N. The SARC Architecture. IEEE Micro 30, 16-29 (2010).
Etsion, Y., Cabarcas, F., Rico, A., Ramirez, A., Badia, R.M., Ayguadé, E., Labarta, J. & Valero, M. Task Superscalar: An Out-of-Order Task Pipeline. IEEE/ACM Intl. Symp. on Microarchitecture (MICRO-43) 89-100 (2010).at <>
Cabarcas, F., Rico, A., Ródenas, D., Martorell, X., Ramirez, A. & Ayguadé, E. A module based Cell processor simulator. 2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06) (2006).