Publications

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2012
Radojkovic, P., Cakarevic, V., Moretó, M., Verdú, J., Pajuelo, A., Cazorla, F.J., Nemirovsky, M. & Valero, M. Optimal Task Assignment in Multithreaded Processors: A Statistical Approach. 17th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-2012) (2012).at <http://capinfo.e.ac.upc.edu/PDFs/dir00/file003944.pdf>
Radojkovic, P., Cakarevic, V., Verdú, J., Pajuelo, A., Cazorla, F.J., Nemirovsky, M. & Valero, M. Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors. IEEE Transactions on Parallel and Distributed Systems XX, (2012).
2011
Ramírez, T., Santana, O.J., Pajuelo, A. & Valero, M. Efficient runahead threads. (2011).
2010
Cazorla, F., Pajuelo, A., Santana, O.J., Fernandez, E. & Valero, M. On the Problem of Evaluating the Performance of Multiprogrammed Workloads. . IEEE Transactions on Computers 59, (2010).
Radojkovic, P., Cakarevic, V., Verdú, J., Pajuelo, A., Cazorla, F., Nemirovsky, M. & Valero, M. Thread to Strand Binding of Parallel Network Applications in Massive Multi-Threaded Systems. (2010).
2009
Cakarevic, V., Radojkovic, P., Verdú, J., Pajuelo, A., Cazorla, F., Nemirovsky, M. & Valero, M. Characterizing the resource-sharing levels in the UltraSPARC T2 Processor. (2009).
2008
Radojkovic, P., Cakarevic, V., Verdú, J., Pajuelo, A., Gioiosa, R., Cazorla, F., Nemirovsky, M. & Valero, M. Measuring Operating System Overhead on CMT Processors. (2008).
Cakarevic, V., Radojkovic, P., Verdú, J., Pajuelo, A., Gioiosa, R., Cazorla, F., Nemirovsky, M. & Valero, M. Understanding the overhead of the spin-lock loop in CMT architectures. (2008).
2007
Vera, J., Cazorla, F., Pajuelo, A., Santana, O.J., Fernández, E. & Valero, M. FAME: FAirly MEasuring Multithreaded Architectures. (2007).at <http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4336221>
Vera, J., Cazorla, F., Pajuelo, A., Santana, O.J., Fernández, E. & Valero, M. Measuring the Performance of Multithreaded Processors. (2007).
2006
González, I., Santana, O.J., Pajuelo, A. & Valero, M. A First Glance at the Implementation of Precise Recoveries in Out-of-order Commit Processors. (2006).
González, I., Santana, O.J., Pajuelo, A. & Valero, M. Implementando recuperaciones precisas en procesadores con consolidación fuera de orden. (2006).
Ramírez, T., Cristal, A., Santana, O.J., Pajuelo, A. & Valero, M. Kilo-Instruction Processors, RunAhead and Prefetch. ACM International Conference on Computing Frontiers (CF 2006) (2006).at <http://capinfo.e.ac.upc.edu/PDFs/dir05/file003137.pdf>
Vera, J., Cazorla, F., Pajuelo, A., Santana, O.J., Fernández, E. & Valero, M. Looking for novel ways to obtain fair measurements in multithreaded architectures. (2006).
Vera, J., Cazorla, F., Pajuelo, A., Santana, O.J., Fernández, E. & Valero, M. A Novel Evaluation Methodology to Obtain Fair Measurements in Multithreaded Architectures. (2006).
2005
Pajuelo, A., González, A. & Valero, M. Control-Flow Independence Reuse via Dynamic Vectorization. (2005).
Ramírez, T., Cristal, A., Pajuelo, A., Santana, O.J. & Valero, M. Eficacia vs. Eficiencia: Una decisión de diseño en Runahead. XVI Jornadas de Paralelismo (2005).at <http://capinfo.e.ac.upc.edu/PDFs/dir01/file003075.pdf>
Pajuelo, A., González, A. & Valero, M. Speculative Execution for Hiding Memory Latency. (2005).
2004
Pajuelo, A., González, A. & Valero, M. Aggressive Speculative Execution for Hidding Memory Latency. (2004).
Pajuelo, A., González, A. & Valero, M. Speculative Execution for Hiding Memory Latency. (2004).