Publications

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Rico, A., Ramirez, A. & Valero, M. Trace Filtering of Multithreaded Applications for CMP Memory Simulation. IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2013) 134–135 (2013).
Ramirez, A., Larriba-Pey, J. L. & Valero, M. Trace Cache Redundancy: Red & Blue Traces. Sixth International Symposium on High-Performance Computer Architecture (HPCA'2000) 325-333 (2000).
Ramirez, A. et al. Trace Cache Redundancy. X Jornadas de Paralelismo 39-44 (1999).
Falcón, A., Santana, O. J., Ramirez, A. & Valero, M. Tolerating branch predictor latency on SMT. 5th International Symposium on High Performance Computing (ISHPC-V) 86-98 (2003).
Fernández, E. et al. Throughput versus Quality of Service in SMT processors. Euromicro-DSD (Digital System Design) (2004).
Acosta, C., Cazorla, F., Ramirez, A. & Valero, M. Thread to Core Assignment in SMT On-Chip Multiprocessors. 21st International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'09) (2009).
Etsion, Y. et al. Task Superscalar: Using Processors as Functional Units. USENIX Workshop on Hot Topics In Parallelism (HotPar) (2010).
Etsion, Y. et al. Task Superscalar: An Out-of-Order Task Pipeline. IEEE/ACM Intl. Symp. on Microarchitecture (MICRO-43) 89-100 (2010). at <http://dx.doi.org/10.1109/MICRO.2010.13>
Rico, A., Ramirez, A. & Valero, M. Task Management Analysis on the Cell BE. XIX Jornadas de Paralelismo, pp. 271-276, Castellón (Spain) 271-276 (2008).
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Rajovic, N. et al. Supercomputing with commodity CPUs: are mobile SoCs ready for HPC?. SC13: International Conference for High Performance Computing, Networking, Storage and Analysis 40–40 (2013).
Falcón, A. et al. Studying New Ways for Improving Adaptive History Length Branch Predictors. 4th International Symposium on High Performance Computing (ISHPC-4) 271-279 (2002).
Carpenter, P., Ródenas, D., Martorell, X., Ramirez, A. & Ayguadé, E. A Streaming Machine Description and Programming Model. 7th Intl. Workshop on Embedded Computer Systems: Architectures, MOdeling, and Simulation (SAMOS VII) 107-116 (2007).
Ramirez, A., Larriba-Pey, J. L. & Valero, M. A Stream Processor Front-end. IEEE Technical Committee on Computer Architecture Newsletter 10-13 (2000).
Santana, O. J., Falcón, A., Ramirez, A. & Valero, M. Stream Predictor Guided Instruction Decoding. XV Jornadas de Paralelismo 184-189 (2004).
Carpenter, P., Ramirez, A. & Ayguadé, E. Starsscheck: a tool to find errors in task-based parallel programs. 16th international Euro-Par conference on Parallel processing 2-13 (2010). at <http://portal.acm.org/citation.cfm?id=1887695.1887698>
Ramirez, A., Larriba-Pey, J. L., Navarro, C., Valero, M. & Torrellas, J. Software Trace Cache for Commercial Applications. International Journal of Parallel Programming 30, 373-395 (2002).
Ramirez, A., Larriba-Pey, J. L., Navarro, C., Torrellas, J. & Valero, M. Software Trace Cache. International Conference on Supercomputing (ICS'1999) 119-126 (1999).
Ramirez, A., Larriba-Pey, J. L. & Valero, M. Software Trace Cache. IEEE Transactions on Computers 54, 22-35 (2005).
González, J. et al. Simulating Whole Supercomputer Applications. IEEE Micro 31, 32-45 (2011).
Ramirez, A., Larriba-Pey, J. L. & Valero, M. Semi-static Branch Prediction for Optimized Code Layouts. 3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3) (2000).
Falcón, A., Santana, O. J., Ramirez, A. & Valero, M. Selecting Where to Simulate SPEC2000 Using Streams Analysis. XV Jornadas de Paralelismo 208--213 (2004).
Sánchez, F., Cabarcas, F., Ramirez, A. & Valero, M. Scalable multicore architectures for long DNA sequence comparison. Concurrency and Computation Practice and Experience 23, (2011).
Álvarez, M., Ramirez, A., Meenderinck, C., Juurlink, B. & Valero, M. Scalability of Macroblock-level parallelism for H.264 decoding. The Fifteenth International Conference on Parallel and Distributed Systems (ICPADS'09) (2009).
Álvarez, M., Ramirez, A., Martorell, X., Ayguadé, E. & Valero, M. Scalability of Macroblock-level Parallelism for H.264 Decoding. Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008, Poster 59-62 (2008).
Sánchez, F., Álvarez, M., Salami, E., Ramirez, A. & Valero, M. On the Scalability of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications. 2005 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2005) 167-176 (2005). at <http://www.bsc.es/media/404.pdf>
Ciobanu, C., Martorell, X., Kuzmanov, G. K., Ramirez, A. & Gaydadjiev, G. N. Scalability Evaluation of a Polymorphic Register File: A CG Case Study. Architecture of Computing Systems - ARCS 2011 13-25 (2011). doi:10.1007/978-3-642-19137-4.
Álvarez, M., Sánchez, F., Salami, E., Ramirez, A. & Valero, M. Scalability and Complexity of 2-Dimensional SIMD Extensions. XV Jornadas de Paralelismo 190-195 (2004).
Isaza, S., Sánchez, F., Gaydadjiev, G. N., Ramirez, A. & Valero, M. Scalability Analysis of Progressive Alignment on a Multicore. Fourth International Conference on Complex, Intelligent and Software Intensive Systems (CISIS '10) 889-894 (2010). at <http://dx.doi.org/10.1109/CISIS.2010.149>
Isaza, S., Sánchez, F., Gaydadjiev, G. N., Ramirez, A. & Valero, M. Scalability Analysis of Progressive Alignment in a Multicore. International Workshop on Multi-Core Computing Systems (MuCoCoS 2010) (2010).
Ramirez, A. et al. The SARC Architecture. IEEE Micro 30, 16-29 (2010).
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Falcón, A., Stark, J., Ramirez, A., Lai, K. & Valero, M. Prophet/Critic Hybrid Branch Prediction. 31st Annual International Symposium on Computer Architecture (ISCA-31) 250-262 (2004).
Ciesko, J. et al. Programmable and Scalable Reductions on Clusters. The 27th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2013) 560–568 (2013).
Cazorla, F. et al. On the Problem of Minimizing Workload Execution Time in SMT Processors. International Conference on Embedded Computer Systems: Architectures, Modelling, and Simulation (SAMOS VII) 66-73 (2007). at <http://dx.doi.org/10.1109/ICSAMOS.2007.4285735>
Isaza, S., Sánchez, F., Gaydadjiev, G. N., Ramirez, A. & Valero, M. Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications. Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS'08) 53-64 (2008).
González, S. et al. Prediction of regulatory regions using ReLA". 16th Annual International Conference on Research in Computational Molecular Biology. 16th Annual International Conference on Research in Computational Molecular Biology, RECOMB (2012).
Santana, O. J., Ramirez, A. & Valero, M. Predicting two Streams per Cycle. XVI Jornadas de Paralelismo 3-10 (2005).
Cazorla, F. et al. Predictable Performance in SMT processors: Synergy Between the OS and SMTs. IEEE Transactions on Computers 55, 785-799 (2006).
Cazorla, F. et al. Predictable Performance in SMT Processors. Computing Frontiers (CF'04) (2004).
Karthikeyan, S., Carpenter, P. & Ramirez, A. Power/Performance evaluation of Energy Efficient Ethernet (EEE) for High Performance Computing. IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2013) (2013).
Navarro, C., Ramirez, A., Larriba-Pey, J. L. & Valero, M. On the Performance of Fetch Engines Running DSS Workloads. 6th International Euro-Par Conference (EuroPar'2000) 591-595 (2000).
Ramirez, A., Prat, O., Labarta, J. & Valero, M. Performance Impact of the Interconnection Network on MareNostrum Applications. 1st Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC 2007) (2007).
Álvarez, M. et al. Performance Evaluation of Macroblock-level Parallelization of H.264 Decoding on a cc-NUMA Multiprocessor Architecture. 4CCC. 4th Colombian Computing Conference, Bucaramanga (Colombia) (2010).
Álvarez, M. et al. Performance Evaluation of Macroblock-level Parallelization of H.264 Decoding on a cc-NUMA Multiprocessor Architecture. Avances en Sistemas e Informática 6, 219-228 (2009).
Álvarez, M., Salami, E., Ramirez, A. & Valero, M. A Performance Evaluation of High Definition Digital Video Decoding Using the H.264/AVC Standard. ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems 255-258 (2005).

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