Publications

Export 153 results:
Author [ Title(Asc)] Type Year
Filters: Author is Alex Ramirez  [Clear All Filters]
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 
T
A. Rico, Ramirez, A., and Valero, M., Trace Filtering of Multithreaded Applications for CMP Memory Simulation, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2013). Austin, United States, pp. 134–135, 2013.
A. Ramirez, Larriba-Pey, J. L., and Valero, M., Trace Cache Redundancy: Red & Blue Traces, Sixth International Symposium on High-Performance Computer Architecture (HPCA'2000). pp. 325-333, 2000.
A. Ramirez, Larriba-Pey, J. L., Navarro, C., Serrano, X., Torrellas, J., and Valero, M., Trace Cache Redundancy, X Jornadas de Paralelismo. pp. 39-44, 1999.
A. Falcón, Santana, O. J., Ramirez, A., and Valero, M., Tolerating branch predictor latency on SMT, 5th International Symposium on High Performance Computing (ISHPC-V). Tokio (Japan), pp. 86-98, 2003.
E. Fernández, Cazorla, F., Ramirez, A., Knijnenburg, P., Sakellariou, R., and Valero, M., Throughput versus Quality of Service in SMT processors, Euromicro-DSD (Digital System Design). Euromicro-DSD (Digital System Design), 2004.
C. Acosta, Cazorla, F., Ramirez, A., and Valero, M., Thread to Core Assignment in SMT On-Chip Multiprocessors, 21st International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'09). 2009.
Y. Etsion, Ramirez, A., Badia, R. M., Ayguadé, E., Labarta, J., and Valero, M., Task Superscalar: Using Processors as Functional Units, USENIX Workshop on Hot Topics In Parallelism (HotPar). 2010.
Y. Etsion, Cabarcas, F., Rico, A., Ramirez, A., Badia, R. M., Ayguadé, E., Labarta, J., and Valero, M., Task Superscalar: An Out-of-Order Task Pipeline, IEEE/ACM Intl. Symp. on Microarchitecture (MICRO-43). pp. 89-100, 2010.
A. Rico, Ramirez, A., and Valero, M., Task Management Analysis on the Cell BE, XIX Jornadas de Paralelismo, pp. 271-276, Castellón (Spain). pp. 271-276, 2008.
S
N. Rajovic, Carpenter, P., Gelado, I., Puzovic, N., Ramirez, A., and Valero, M., Supercomputing with commodity CPUs: are mobile SoCs ready for HPC?, SC13: International Conference for High Performance Computing, Networking, Storage and Analysis. Denver, United States, pp. 40–40, 2013.
A. Falcón, Santana, O. J., Medina, P., Fernández, E., Ramirez, A., and Valero, M., Studying New Ways for Improving Adaptive History Length Branch Predictors, 4th International Symposium on High Performance Computing (ISHPC-4). Kansai Science City (Japan), pp. 271-279, 2002.
P. Carpenter, Ródenas, D., Martorell, X., Ramirez, A., and Ayguadé, E., A Streaming Machine Description and Programming Model, 7th Intl. Workshop on Embedded Computer Systems: Architectures, MOdeling, and Simulation (SAMOS VII). Springer-Verlag, pp. 107-116, 2007.
A. Ramirez, Larriba-Pey, J. L., and Valero, M., A Stream Processor Front-end, IEEE Technical Committee on Computer Architecture Newsletter. pp. 10-13, 2000.
O. J. Santana, Falcón, A., Ramirez, A., and Valero, M., Stream Predictor Guided Instruction Decoding, XV Jornadas de Paralelismo. pp. 184-189, 2004.
P. Carpenter, Ramirez, A., and Ayguadé, E., Starsscheck: a tool to find errors in task-based parallel programs, 16th international Euro-Par conference on Parallel processing. pp. 2-13, 2010.
A. Ramirez, Larriba-Pey, J. L., Navarro, C., Valero, M., and Torrellas, J., Software Trace Cache for Commercial Applications, International Journal of Parallel Programming, vol. 30, no. 5. pp. 373-395, 2002.
A. Ramirez, Larriba-Pey, J. L., Navarro, C., Torrellas, J., and Valero, M., Software Trace Cache, International Conference on Supercomputing (ICS'1999). pp. 119-126, 1999.
A. Ramirez, Larriba-Pey, J. L., and Valero, M., Software Trace Cache, IEEE Transactions on Computers, vol. 54, no. 1. pp. 22-35, 2005.
J. González, Giménez, J., Casas, M., Moretó, M., Ramirez, A., Labarta, J., and Valero, M., Simulating Whole Supercomputer Applications, IEEE Micro, vol. 31. IEEE, pp. 32-45, 2011.
A. Ramirez, Larriba-Pey, J. L., and Valero, M., Semi-static Branch Prediction for Optimized Code Layouts, 3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3). 2000.
A. Falcón, Santana, O. J., Ramirez, A., and Valero, M., Selecting Where to Simulate SPEC2000 Using Streams Analysis, XV Jornadas de Paralelismo. p. 208--213, 2004.
F. Sánchez, Cabarcas, F., Ramirez, A., and Valero, M., Scalable multicore architectures for long DNA sequence comparison, Concurrency and Computation Practice and Experience, vol. 23, no. 17. 2011.
M. Álvarez, Ramirez, A., Meenderinck, C., Juurlink, B., and Valero, M., Scalability of Macroblock-level parallelism for H.264 decoding, The Fifteenth International Conference on Parallel and Distributed Systems (ICPADS'09). Shenzhen (China), 2009.
M. Álvarez, Ramirez, A., Martorell, X., Ayguadé, E., and Valero, M., Scalability of Macroblock-level Parallelism for H.264 Decoding, Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008, Poster. pp. 59-62, 2008.
F. Sánchez, Álvarez, M., Salami, E., Ramirez, A., and Valero, M., On the Scalability of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications, 2005 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2005). pp. 167-176, 2005.
C. Ciobanu, Martorell, X., Kuzmanov, G. K., Ramirez, A., and Gaydadjiev, G. N., Scalability Evaluation of a Polymorphic Register File: A CG Case Study, Architecture of Computing Systems - ARCS 2011. Springer-Verlag Berlin Heidelberg, pp. 13-25, 2011.
M. Álvarez, Sánchez, F., Salami, E., Ramirez, A., and Valero, M., Scalability and Complexity of 2-Dimensional SIMD Extensions, XV Jornadas de Paralelismo. pp. 190-195, 2004.
S. Isaza, Sánchez, F., Gaydadjiev, G. N., Ramirez, A., and Valero, M., Scalability Analysis of Progressive Alignment on a Multicore, Fourth International Conference on Complex, Intelligent and Software Intensive Systems (CISIS '10). pp. 889-894, 2010.
S. Isaza, Sánchez, F., Gaydadjiev, G. N., Ramirez, A., and Valero, M., Scalability Analysis of Progressive Alignment in a Multicore, International Workshop on Multi-Core Computing Systems (MuCoCoS 2010). Krakow (Poland), 2010.
A. Ramirez, Cabarcas, F., Juurlink, B., Mesa, M. A., Sánchez, F., Azevedo, A., Meenderinck, C., Ciobanu, C., Isaza, S., and Gaydadjiev, G. N., The SARC Architecture, IEEE Micro, vol. 30, no. 5. pp. 16-29, 2010.
P
A. Falcón, Stark, J., Ramirez, A., Lai, K., and Valero, M., Prophet/Critic Hybrid Branch Prediction, 31st Annual International Symposium on Computer Architecture (ISCA-31). pp. 250-262, 2004.
J. Ciesko, Bueno-Hedo, J., Puzovic, N., Ramirez, A., Badia, R. M., and Labarta, J., Programmable and Scalable Reductions on Clusters, The 27th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2013). IEEE, Boston, United States, pp. 560–568, 2013.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A., and Valero, M., On the Problem of Minimizing Workload Execution Time in SMT Processors, International Conference on Embedded Computer Systems: Architectures, Modelling, and Simulation (SAMOS VII). Samos, Greece, pp. 66-73, 2007.
S. Isaza, Sánchez, F., Gaydadjiev, G. N., Ramirez, A., and Valero, M., Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications, Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS'08). pp. 53-64, 2008.
S. González, Montserrat, B., Sánchez, F., Puiggros, M., Blanco, E., Martinez, L., Ramirez, A., and Torrents, D., Prediction of regulatory regions using ReLA". 16th Annual International Conference on Research in Computational Molecular Biology, 16th Annual International Conference on Research in Computational Molecular Biology, RECOMB. 2012.
O. J. Santana, Ramirez, A., and Valero, M., Predicting two Streams per Cycle, XVI Jornadas de Paralelismo. pp. 3-10, 2005.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A., and Valero, M., Predictable Performance in SMT processors: Synergy Between the OS and SMTs, IEEE Transactions on Computers, vol. 55, no. 7. pp. 785-799, 2006.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A., and Valero, M., Predictable Performance in SMT Processors, Computing Frontiers (CF'04). 2004.
S. Karthikeyan, Carpenter, P., and Ramirez, A., Power/Performance evaluation of Energy Efficient Ethernet (EEE) for High Performance Computing, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2013). Austin, United States, 2013.
C. Navarro, Ramirez, A., Larriba-Pey, J. L., and Valero, M., On the Performance of Fetch Engines Running DSS Workloads, 6th International Euro-Par Conference (EuroPar'2000). Springer-Verlag, pp. 591-595, 2000.
A. Ramirez, Prat, O., Labarta, J., and Valero, M., Performance Impact of the Interconnection Network on MareNostrum Applications, 1st Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC 2007). 2007.
M. Álvarez, Ramirez, A., Valero, M., Azevedo, A., Meenderinck, C., and Juurlink, B., Performance Evaluation of Macroblock-level Parallelization of H.264 Decoding on a cc-NUMA Multiprocessor Architecture, 4CCC. 4th Colombian Computing Conference, Bucaramanga (Colombia). 2010.
M. Álvarez, Ramirez, A., Valero, M., Azevedo, A., Meenderinck, C., and Juurlink, B., Performance Evaluation of Macroblock-level Parallelization of H.264 Decoding on a cc-NUMA Multiprocessor Architecture, Avances en Sistemas e Informática, vol. 6, no. 1. pp. 219-228, 2009.
M. Álvarez, Salami, E., Ramirez, A., and Valero, M., A Performance Evaluation of High Definition Digital Video Decoding Using the H.264/AVC Standard, ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. pp. 255-258, 2005.

Pages