Publications

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2003
F. Cazorla, Fernández, E., Ramirez, A., and Valero, M., Improving Memory Latency Aware Fetch Policies for SMT Processors, 5th International Symposium on High Performance Computing (ISHPC-V). Springer-Verlag, Tokyo, Japan, pp. 70-85, 2003.
2004
F. Cazorla, Fernández, E., Ramirez, A., and Valero, M., Approaching a Smart Sharing of Resources in SMT Processors, Workshop on Complexity-Effective Design (WCED). 2004.
F. Cazorla, Fernández, E., Ramirez, A., and Valero, M., DCache Warn: An I-Fetch Policy To Increase SMT Efficiency, 18th International Parallel and Distributed Processing Symposium (IPDPS-2004). IEEE Computer Society Press, 2004.
F. Cazorla, Ramirez, A., Valero, M., and Fernández, E., Dynamically Controlled Resource Allocation in SMT Processors, 37th Annual International Symposium on Microarchitecture (MICRO-37). pp. 171-182, 2004.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernandez, E., Ramirez, A., and Valero, M., Enabling SMT for Real-Time Embedded Systems., European Signal Processing Conference (EUSIPCO). 2004.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernandez, E., Ramirez, A., and Valero, M., Feasibility of QoS for SMT by Resource Allocation., Lecture Notes in Computer Science (LNCS) , vol. 3149/2004. 2004.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A., and Valero, M., Implicit vs. Explicit Resource Allocation in SMT Processors, 2004 Euromicro Symposium on Digital Systems Design (DSD 2004). Rennes, France, pp. 44-51, 2004.
F. Cazorla, Fernández, E., Ramirez, A., and Valero, M., Optimizing Long-Latency-Load-Aware Fetch Policies for SMT Processors, International Journal of High Performance Computing and Networking (IJHPCN), vol. 2, no. 2. 2004.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A., and Valero, M., Predictable Performance in SMT Processors, Computing Frontiers (CF'04). 2004.
F. Cazorla, Ramirez, A., Valero, M., Knijnenburg, P., Sakellariou, R., and Fernández, E., QoS for High-Performance SMT Processors in Embedded Systems, IEEE Micro, vol. 24. pp. 24-31, 2004.
E. Fernández, Cazorla, F., Ramirez, A., Knijnenburg, P., Sakellariou, R., and Valero, M., Throughput versus Quality of Service in SMT processors, Euromicro-DSD (Digital System Design). Euromicro-DSD (Digital System Design), 2004.
2006
K. Kedzierski, Cazorla, F., and Valero, M., Analysis of multithreading capabilities of current high-performance processors. XVII Jornadas de Paralelismo, 2006.
K. Kedzierski, Cazorla, F., and Valero, M., Analysis of Simultaneous Multithreading Implementations in Current High-Performance Processors. ACACES 2006, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, 2006.
M. Pericàs, Cristal, A., González, R., Cazorla, F., Jiménez, D. A., and Valero, M., Boosting ILP{&}TLP with the Flexible Multi-Core (FMC), 2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06). Academia Press, L'Aquila, Italy, pp. 125–128, 2006.
C. Boneti, Cazorla, F., and Valero, M., Improving EDF for SMT processors. XVII Jornadas de Paralelismo, 2006.
J. Vera, Cazorla, F., Pajuelo, A., Santana, O. J., Fernández, E., and Valero, M., Looking for novel ways to obtain fair measurements in multithreaded architectures. XVII Jornadas de Paralelismo, 2006.
J. Vera, Cazorla, F., Pajuelo, A., Santana, O. J., Fernández, E., and Valero, M., A Novel Evaluation Methodology to Obtain Fair Measurements in Multithreaded Architectures. In Workshop on Modeling, Benchmarking and Simulation (MoBS)2006. Held in conjunction with ISCA, Boston, USA, 2006.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A., and Valero, M., Predictable Performance in SMT processors: Synergy Between the OS and SMTs, IEEE Transactions on Computers, vol. 55, no. 7. pp. 785-799, 2006.
2007
C. Acosta, Cazorla, F., Ramirez, A., and Valero, M., Core to Memory Interconnection Implications for Forthcoming On-Chip Multiprocessors, 1st Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI 2007). 2007.
M. Moreto, Cazorla, F., Ramirez, A., and Valero, M., Explaining Dynamic Cache Partitioning Speed Ups, IEEE Computer Architecture Letters, vol. 6, no. 1. pp. 1-12, 2007.
J. Vera, Cazorla, F., Pajuelo, A., Santana, O. J., Fernández, E., and Valero, M., FAME: FAirly MEasuring Multithreaded Architectures. Brasov, Romania, 2007.
M. Pericàs, Cristal, A., Cazorla, F., González, R., Jiménez, D., and Valero, M., A Flexible Heterogeneous Multi-Core Architecture, The 2007 International Conference on Parallel Architectures and Compilation Techniques (PACT 2007). Brasov, Romania, pp. 13–24, 2007.
J. Vera, Cazorla, F., Pajuelo, A., Santana, O. J., Fernández, E., and Valero, M., Measuring the Performance of Multithreaded Processors. In SPEC Benchmark Workshop (in conjunction with the Annual Meeting of the Standard Performance Evaluation Corporation (SPEC)), Austin, USA, 2007.
M. Moreto, Cazorla, F., Ramirez, A., and Valero, M., MLP-aware dynamic cache partitioning, International Conference on Parallel Architectures and Compilation Techniques (PACT). Brasov, Romania, pp. 418-418, 2007.
M. Moreto, Cazorla, F., Ramirez, A., and Valero, M., Online Prediction of Applications Cache Utility, International Symposium on Systems, Architectures, MOdeling and Simulation (SAMOS). IEEE Computer Society Press, pp. 169-177, 2007.
M. Moreto, Cazorla, F., Ramirez, A., and Valero, M., Online Prediction of Throughput for Different Cache Sizes, XVIII Jornadas de Paralelismo. Zaragoza, Spain, 2007.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A., and Valero, M., On the Problem of Minimizing Workload Execution Time in SMT Processors, International Conference on Embedded Computer Systems: Architectures, Modelling, and Simulation (SAMOS VII). Samos, Greece, pp. 66-73, 2007.
2008
P. A. Castillo, Mora, A. M., Merelo, J. J., Laredo, J. L., Moreto, M., Cazorla, F., Valero, M., and McKee, S. A., Architecture performance prediction using evolutionary artificial neural networks. In European Workshop on Hardware Optimization Techniques (EVOHot). Napoli, Italy, 2008.
C. Boneti, Cazorla, F., Gioiosa, R., Corbalán, J., Labarta, J., and Valero, M., Balancing HPC Applications Through Smart Allocation of Resources in MT Processors. Miami, Florida, USA, 2008.
M. Moreto, Cazorla, F., Ramirez, A., and Valero, M., Dynamic Cache Partitioning Based on the MLP on Cache Misses., Transactions on HiPEAC, vol. 3, no. 1. pp. 1-21, 2008.
C. Boneti, Gioiosa, R., Cazorla, F., and Valero, M., A Dynamic Scheduler for Balancing HPC Applications. Austin, USA, 2008.
P. A. Castillo, Merelo, J. J., Moreto, M., Cazorla, F., Valero, M., Mora, A. M., Laredo, J. L., and McKee, S. A., Evolutionary system for prediction and optimization of hardware architecture performance. In IEEE Congress on Evolutionary Computation (CEC). Hong Kong, 2008.
P. Radojkovic, Cakarevic, V., Verdú, J., Pajuelo, A., Gioiosa, R., Cazorla, F., Nemirovsky, M., and Valero, M., Measuring Operating System Overhead on CMT Processors. In 20th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). Campo Grande, Brazil, 2008.
C. Acosta, Cazorla, F., Ramirez, A., and Valero, M., MFLUSH: Handling Long-latency loads in SMT On-Chip Multiprocessors., International Conference on Parallel Processing (ICPP). pp. 173-181, 2008.
M. Moreto, Cazorla, F., Ramirez, A., and Valero, M., MLP-aware dynamic cache partitioning, 2008 International Conference on High Performance Embedded Architectures & Compilers (HiPEAC 2008). Goteborg, Sweden, pp. 337-352, 2008.
K. J. Nesbit, Moreto, M., Cazorla, F., Ramirez, A., Valero, M., and Smith, J. E., Multicore Resource Management, IEEE Micro, vol. 28, no. 3. pp. 6-16, 2008.
C. Boneti, Cazorla, F., Gioiosa, R., and Valero, M., Scheduling Real-Time Systems With Explicit Resource Allocation Processors. In International Conference on Architecture of Computing Systems (ARCS). Dresden, Germany, 2008.
J. J. Alastruey, Cazorla, F., Monreal, T., Viñals, V., and Valero, M., Selection of the Register File Size and the Resource Allocation Policy on SMT Processors. In 20th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). Campo Grande, Brazil, 2008.
C. Boneti, Cazorla, F., Gioiosa, R., Cher, C. - Y., Buyuktosunoglu, A., and Valero, M., Software-Controlled Priority Characterization of POWER5 Processor. Beijing, China, 2008.
M. Pericàs, Cristal, A., Cazorla, F., González, R., Veidenbaum, A., Jiménez, D. A., and Valero, M., A Two-Level Load/Store Queue Based on Execution Locality, The 35th International Symposium on Computer Architecture (ISCA 2008). The Institute of Electrical and Electronics Engineers, Inc., Beijing, China, pp. 25–36, 2008.
M. Pericas, González, R., Cazorla, F., Cristal, A., Veidenbaum, A., Jiménez, D. A., and Valero, M., A two-level Load/Store Queue based on Execution Locality. In International Symposium on Computer Architecture. Beijing, China, 2008.
V. Cakarevic, Radojkovic, P., Verdú, J., Pajuelo, A., Gioiosa, R., Cazorla, F., Nemirovsky, M., and Valero, M., Understanding the overhead of the spin-lock loop in CMT architectures. In Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA). Beijing, China, 2008.
K. J. Nesbit, Moreto, M., Cazorla, F., Ramirez, A., Valero, M., and Smith, J. E., Virtual Private Machines: Hardware/Software Interactions in the Multicore Era. IEEE Micro, special issue on Interaction of Computer Architecture and Operating System in the Manycore Era, vol. 38, no. 3, 2008.

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