Publications

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2004
Cazorla, F., Fernández, E., Ramirez, A. & Valero, M. Approaching a Smart Sharing of Resources in SMT Processors. Workshop on Complexity-Effective Design (WCED) (2004).
Cazorla, F., Fernández, E., Ramirez, A. & Valero, M. DCache Warn: An I-Fetch Policy To Increase SMT Efficiency. 18th International Parallel and Distributed Processing Symposium (IPDPS-2004) (2004).
Cazorla, F., Ramirez, A., Valero, M. & Fernández, E. Dynamically Controlled Resource Allocation in SMT Processors. 37th Annual International Symposium on Microarchitecture (MICRO-37) 171-182 (2004).
Cazorla, F. et al. Enabling SMT for Real-Time Embedded Systems. European Signal Processing Conference (EUSIPCO) (2004).
Cazorla, F. et al. Feasibility of QoS for SMT by Resource Allocation. Lecture Notes in Computer Science (LNCS) 3149/2004, (2004).
Cazorla, F. et al. Implicit vs. Explicit Resource Allocation in SMT Processors. 2004 Euromicro Symposium on Digital Systems Design (DSD 2004) 44-51 (2004).
Cazorla, F., Fernández, E., Ramirez, A. & Valero, M. Optimizing Long-Latency-Load-Aware Fetch Policies for SMT Processors. International Journal of High Performance Computing and Networking (IJHPCN) 2, (2004).
Cazorla, F. et al. Predictable Performance in SMT Processors. Computing Frontiers (CF'04) (2004).
Cazorla, F. et al. QoS for High-Performance SMT Processors in Embedded Systems. IEEE Micro 24, 24-31 (2004).
Fernández, E. et al. Throughput versus Quality of Service in SMT processors. Euromicro-DSD (Digital System Design) (2004).
2005
Cazorla, F. et al. Architectural Support for Real-Time Task Scheduling in SMT Processors. International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES-2005) (2005).
Cazorla, F., Fernández, E., Ramirez, A. & Valero, M. Dynamically Controlled Resource Allocation in SMT. XVI Jornadas de Paralelismo. Granada (2005).
Cristal, A. et al. Kilo-instruction Processors: Overcoming the Memory Wall. IEEE Micro 25, 48–57 (2005).
Mir, S., Cazorla, F., Ramirez, A. & Valero, M. Metrics for the Evaluation of SMT Processors Performance. XVI Jornadas de Paralelismo (2005).
Cazorla, F. et al. Quality of service for Simultaneous Multithreading Processors. ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems 67-70 (2005).
2007
Acosta, C., Cazorla, F., Ramirez, A. & Valero, M. Core to Memory Interconnection Implications for Forthcoming On-Chip Multiprocessors. 1st Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI 2007) (2007).
Moreto, M., Cazorla, F., Ramirez, A. & Valero, M. Explaining Dynamic Cache Partitioning Speed Ups. IEEE Computer Architecture Letters 6, 1-12 (2007).
Vera, J. et al. FAME: FAirly MEasuring Multithreaded Architectures. (2007). at <http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4336221>
Pericàs, M. et al. A Flexible Heterogeneous Multi-Core Architecture. The 2007 International Conference on Parallel Architectures and Compilation Techniques (PACT 2007) 13–24 (2007). at <http://capinfo.e.ac.upc.edu/PDFs/dir10/file003258.pdf>
Vera, J. et al. Measuring the Performance of Multithreaded Processors. (2007).
Moreto, M., Cazorla, F., Ramirez, A. & Valero, M. MLP-aware dynamic cache partitioning. International Conference on Parallel Architectures and Compilation Techniques (PACT) 418-418 (2007).
Moreto, M., Cazorla, F., Ramirez, A. & Valero, M. Online Prediction of Applications Cache Utility. International Symposium on Systems, Architectures, MOdeling and Simulation (SAMOS) 169-177 (2007).
Moreto, M., Cazorla, F., Ramirez, A. & Valero, M. Online Prediction of Throughput for Different Cache Sizes. XVIII Jornadas de Paralelismo (2007).
Cazorla, F. et al. On the Problem of Minimizing Workload Execution Time in SMT Processors. International Conference on Embedded Computer Systems: Architectures, Modelling, and Simulation (SAMOS VII) 66-73 (2007). at <http://dx.doi.org/10.1109/ICSAMOS.2007.4285735>
2008
Castillo, P. A. et al. Architecture performance prediction using evolutionary artificial neural networks. (2008).
Boneti, C. et al. Balancing HPC Applications Through Smart Allocation of Resources in MT Processors. (2008). at <http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4536293>
Moreto, M., Cazorla, F., Ramirez, A. & Valero, M. Dynamic Cache Partitioning Based on the MLP on Cache Misses. Transactions on HiPEAC 3, 1-21 (2008).
Boneti, C., Gioiosa, R., Cazorla, F. & Valero, M. A Dynamic Scheduler for Balancing HPC Applications. (2008). at <http://portal.acm.org/citation.cfm?id=1413412>
Castillo, P. A. et al. Evolutionary system for prediction and optimization of hardware architecture performance. (2008).
Radojkovic, P. et al. Measuring Operating System Overhead on CMT Processors. (2008).
Acosta, C., Cazorla, F., Ramirez, A. & Valero, M. MFLUSH: Handling Long-latency loads in SMT On-Chip Multiprocessors. International Conference on Parallel Processing (ICPP) 173-181 (2008).
Moreto, M., Cazorla, F., Ramirez, A. & Valero, M. MLP-aware dynamic cache partitioning. 2008 International Conference on High Performance Embedded Architectures & Compilers (HiPEAC 2008) 337-352 (2008).
Nesbit, K. J. et al. Multicore Resource Management. IEEE Micro 28, 6-16 (2008).
Boneti, C., Cazorla, F., Gioiosa, R. & Valero, M. Scheduling Real-Time Systems With Explicit Resource Allocation Processors. (2008).
Alastruey, J. J., Cazorla, F., Monreal, T., Viñals, V. & Valero, M. Selection of the Register File Size and the Resource Allocation Policy on SMT Processors. (2008).
Boneti, C. et al. Software-Controlled Priority Characterization of POWER5 Processor. (2008). at <http://www2.computer.org/portal/web/csdl/doi/10.1109/ISCA.2008.8>
Pericàs, M. et al. A Two-Level Load/Store Queue Based on Execution Locality. The 35th International Symposium on Computer Architecture (ISCA 2008) 25–36 (The Institute of Electrical and Electronics Engineers, Inc., 2008). at <http://capinfo.e.ac.upc.edu/PDFs/dir05/file003514.pdf>
Pericas, M. et al. A two-level Load/Store Queue based on Execution Locality. (2008).
Cakarevic, V. et al. Understanding the overhead of the spin-lock loop in CMT architectures. (2008).
Nesbit, K. J. et al. Virtual Private Machines: Hardware/Software Interactions in the Multicore Era. (2008).

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