Publications

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2012
Dickov, B., Pericàs, M., Houzeaux, G., Navarro, N. & Ayguadé, E. Assessing the impact of network compression on Molecular Dynamics and Finite Element Methods. 14th International Conference on High-Performance Computing and Communications (HPCC-2012) (2012).
Shafiq, M., Pericàs, M., Navarro, N. & Ayguadé, E. BSArc: Blacksmith Streaming Architecture for HPC Accelerators. ACM International Conference on Computing Frontiers (2012).
Bertran, R., González, M., Martorell, X., Navarro, N. & Ayguadé, E. Counter-Based Power Modeling Methods: Top-Down vs. Bottom-Up. The Computer Journal (2012).doi:10.1093/comjnl/bxs116
Bertran, R., Becerra, Y., Carrera, D., n, V.Ã.§ B., González, M., Martorell, X., Navarro, N., Torres, J. & Ayguadé, E. Energy accounting for shared virtualized environments under DVFS using PMC-based power models. Future Generation Computer Systems 28, 457 - 468 (2012).
Álvarez, L., Vilanova, L., González, M., Martorell, X., Navarro, N. & Ayguadé, E. Hardware-software coherence protocol for the coexistence of caches and local memories. Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis 89:1–89:11 (2012).at <http://dl.acm.org/citation.cfm?id=2388996.2389117>
Hussain, T., Navarro, N., Ayguadé, E. & Pericàs, M. PPMC : Hardware Scheduling and Memory Management Support for Multi Accelerators. 22nd International Conference on Field Programmable Logic and Applications (FPL-2012 (2012).
2011
Araya-Polo, M., Cabezas, J., Hanzich, M., Pericas, M., Morancho, E., Gelado, I., Shafiq, M., Rubio, F., Cela, J.M., Ayguadé, E., Navarro, N. & Valero, M. Assessing Accelerator-based HPC Reverse Time Migration. Transactions on Parallel and Distributed Systems, Special Issue on Accelerators 22(1), 147-162 (2011).
Álvarez, L., Bertran, R., González, M., Martorell, X., Navarro, N. & Ayguadé, E. Design space exploration for aggressive core replication schemes in CMPs. Proceedings of the 20th international symposium on High performance distributed computing 269–270 (2011).doi:http://doi.acm.org/10.1145/1996130.1996169
Villavieja, C., Karakostas, V., Vilanova, L., Etsion, Y., Ramirez, A., Mendelson, A., Navarro, N., Cristal, A. & Unsal, O. DiDi: Mitigating The Performance Impact of TLB Shootdowns Using A Shared TLB Directory. Parallel Architectures and Compilation Techniques (PACT) (2011).
Bertran, R., Becerra, Y., Carrera, D., Beltran, V., González, M., Martorell, X., Navarro, N., Torres, J. & Ayguadé, E. Energy accounting for shared virtualized environments under DVFS using PMC-based power models. Future Generation Computer Systems 28, 457 - 468 (2011).
Villavieja, C., Etsion, Y., Ramirez, A. & Navarro, N. FELI: HW/SW support for On-Chip Distributed Shared Memory in Multicores. Euro-Par (2011).
Shafiq, M., Pericàs, M., Navarro, N. & Ayguadé, E. TARCAD: A template architecture for reconfigurable accelerator designs. IEEE Symposium on Application Specific Processors (SASP) 8-15 (2011).
2010
Gelado, I., Stone, J.E., Cabezas, J., Patel, S., Navarro, N. & Hwu, W.-mei An Asymmetric Distributed Shared Memory Model for Heterogeneous Parallel Systems. ACM SIGARCH Computer Architecture News - ASPLOS '10 (2010).at <http://doi.acm.org/10.1145/1735970.1736059>
Bertran, R., González, M., Martorell, X., Navarro, N. & Ayguadé, E. Decomposable and Responsive Power Models for Multicore Processors using Performance Counters. (2010).at <http://doi.acm.org/10.1145/1810085.1810108>
Bertran, R., González, M., Martorell, X., Navarro, N. & Ayguadé, E. Local Memory Design Space Exploration for High-Performance Computing. (2010).at <http://comjnl.oxfordjournals.org/content/early/2010/03/23/comjnl.bxq026.full.pdf+html>
2009
Cabezas, J., Araya-Polo, M., Gelado, I., Navarro, N. & Cela, J.M. High-Performance Reverse Time Migration on GPU. XXVIII International Conference of the Chilean Computer Society - XIII Workshop on Parallel and Distributed Systems (WSDP) (2009).
Jiménez, V.J., Vilanova, L., Gelado, I., Gil, M., Fursin, G. & Navarro, N. Predictive Runtime Code Scheduling for Heterogeneous Architectures. (2009).at <http://dx.doi.org/10.1007/978-3-540-92990-1_4>
2008
Gelado, I., Kelm, J.H., Ryoo, S., Lumetta, S.S., Navarro, N. & Hwu, W.-mei CUBA: an Architecture for Efficient CPU/co-processor Data Communication. 22nd International Conference on Supercomputing (2008).
Gelado, I., Ramirez, A., Navarro, N. & Villavieja, C. Memory Management on Chip-MultiProcessors with on-chip Memories. Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA'08) 1-7 (2008).
Villavieja, C., Gelado, I., Ramirez, A. & Navarro, N. On-Chip memories, the OS perspective. 5th HiPEAC Industrial Workshop (2008).
2007
Bosschere, K.D., Luk, W., Martorell, X., Navarro, N., O'Boyle, M., Pnevmatikatos, D., Ramirez, A., Sainrat, P., Seznec, A., Stenström, P. & Temam, O. High Performance Embedded Architectures and Compilation Roadmap. (2007).
2001
Oliver, J., Guitart, J., Ayguadé, E., Navarro, N. & Torres, J. Strategies for Efficient Exploitation of Loop-Level Parallelism in Java Concurrency and Computation. Concurrency and Computation: Practice and Experience Vol. 13 (8-9), 663-680 (2001).