Publications

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Workshops
M. Valero, Verdú, J., Nemirovsky, M., and García, J., Workload Characterization and Stateful Networking Aplications. ISHPC. International Symposium on High Performance Computers, 2005.
V. Cakarevic, Radojkovic, P., Verdú, J., Pajuelo, A., Gioiosa, R., Cazorla, F., Nemirovsky, M., and Valero, M., Understanding the overhead of the spin-lock loop in CMT architectures. In Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA). Beijing, China, 2008.
N. Miletić, Smiljkovic, V., Perfumo, C., Harris, T., Cristal, A., Hur, I., Unsal, O., and Valero, M., Transactification of a real-world system library, 5th ACM SIGPLAN Workshop on Transactional Computing - TRANSACT 2010. Paris, France, 2010.
V. Smiljkovic, Stipić, S., Unsal, O., Cristal, A., and Valero, M., Transaction Coalescing - Lowering Transactional Overheads by Merging Transactions, Sixth Workshop on Programmability Issues for Heterogeneous Multicores (MULTIPROG-2013). Berlin, Germany, 2013.
J. Verdú, Nemirovsky, M., García, J., and Valero, M., Traffic Aggregation Impact on the Memory Performance of Networking Applications. MEDEA Workshop: ?MEmory performance:DEaling with Applications, systems and architecture?, 2004.
J. Verdú, Nemirovsky, M., García, J., and Valero, M., Te Impact of Traffic Aggregation on the Memory Performance of Networking Applications. Computer Architecture News, 2005.
Y. Etsion, Ramirez, A., Badia, R. M., Ayguadé, E., Labarta, J., and Valero, M., Task Superscalar: Using Processors as Functional Units, USENIX Workshop on Hot Topics In Parallelism (HotPar). 2010.
A. Pajuelo, González, A., and Valero, M., Speculative Execution for Hiding Memory Latency. MEDEA Workshop: ?MEmory performance:DEaling with Applications, systems and architecture, 2004.
T. Ramírez, Pajuelo, M., Santana, O. J., and Valero, M., A Simple Speculative Load Control Mechanism for Energy Saving. MEDEA Workshop: ?MEmory performance:DEaling with Applications, systems and architecture?, 2006.
A. Ramirez, Larriba-Pey, J. L., and Valero, M., Semi-static Branch Prediction for Optimized Code Layouts, 3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3). 2000.
S. Isaza, Sánchez, F., Gaydadjiev, G. N., Ramirez, A., and Valero, M., Scalability Analysis of Progressive Alignment in a Multicore, International Workshop on Multi-Core Computing Systems (MuCoCoS 2010). Krakow (Poland), 2010.
O. J. Santana, Ramirez, A., and Valero, M., Reducing Fetch Architecture Complexity Using Procedure Inlining, 8th Workshop on Interaction between Compilers and Computer Architectures (INTERACT). 2004.
K. Kedzierski, Cazorla, F., Gioiosa, R., Buyuktosunoglu, A., and Valero, M., Power and Performance Aware Reconfigurable Cache for CMPs. Workshop on Next Generation Multicore/Manycore Technologies (IFMT), in conjunction with ISCA, 2010.
A. Ramirez, Prat, O., Labarta, J., and Valero, M., Performance Impact of the Interconnection Network on MareNostrum Applications, 1st Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC 2007). 2007.
N. Markovic, Nemirovsky, D., González, R., Ünsal, O. S., Valero, M., and Cristal, A., Object Orienteed Execution Model (OOM), 2nd Workshop on New Directions in Computer Architecture (NDCA-2) Held in Conjunction with the 38th International Symposium on Computer Architecture (ISCA-38). San Jose, California, Sunday June 5th, 2011.
N. Markovic, Nemirovsky, D., González, R., Unsal, O., Valero, M., and Cristal, A., Object Oriented execution Model (OOM), New Directions in Computer Architecture (NDCA-2). San Jose, California, United States, 2011.
J. Vera, Cazorla, F., Pajuelo, A., Santana, O. J., Fernández, E., and Valero, M., A Novel Evaluation Methodology to Obtain Fair Measurements in Multithreaded Architectures. In Workshop on Modeling, Benchmarking and Simulation (MoBS)2006. Held in conjunction with ISCA, Boston, USA, 2006.
J. Vera, Cazorla, F., Pajuelo, A., Santana, O. J., Fernández, E., and Valero, M., Measuring the Performance of Multithreaded Processors. In SPEC Benchmark Workshop (in conjunction with the Annual Meeting of the Standard Performance Evaluation Corporation (SPEC)), Austin, USA, 2007.
J. J. Alastruey, Monreal, T., Viñals, V., and Valero, M., Limits on Early Release of Physical Registers. XV Jornadas de Paralelismo, 2004.
O. J. Santana, Ramirez, A., and Valero, M., Latency Tolerant Branch Predictors, 2003 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'03). Kauai, Hawaii (United States), pp. 30-39, 2003.
M. Paolieri, Bonesana, I., Gioiosa, R., and Valero, M., J-DSE: Joint Software and Hardware Design Space Exploration for Application Specific Processors. Programmability Issues for Multi-Core Computers (MULTIPROG), 2010.
V. Gajinov, Cristal, A., Milovanovic, M., Ayguadé, E., Unsal, O., and Valero, M., Integrating dataflow abstractions into transactional memory, Systems for Future Multi-Core Architectures (SFMA'11) . 2011.
V. Gajinov, Milovanovic, M., Unsal, O., Cristal, A., Ayguadé, E., and Valero, M., Integrating Dataflow Abstractions into Transactional Memory, First Workshop on Systems for Future Multi-Core Architectures (SFMA'11). Salzburg, Austria, pp. 1–6, 2011.
J. García, March, M., Cerdá, L., Corbal, J., and Valero, M., A Hybrid DRAM/SRAM Design for Fast Packet Buffers. HPRS. IEEE Workshop on High Performance Switching and Routing, 2004.
M. Moreto, Martínez, C., Beivide, R., Vallejo, E., and Valero, M., Hierarchical Gaussian Topologies. ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, 2005.
G. Kestor, Gioiosa, R., Unsal, O., Cristal, A., and Valero, M., Hardware/Software Techniques for Assisted Execution Runtime Systems, The 2nd Workshop on Runtime Environments, Systems, Layering and Virtualized Environments (RESoLVE). 2012.
M. Moreto, Paolieri, M., Abella, J., Quiñones, E., Cazorla, F., and Valero, M., Hard Real-Time Capable Multicore Processors for Space Applications. ESTEC 1st Networking/Partnering Day, 2010.
C. Navarro, Ramirez, A., Larriba-Pey, J. L., and Valero, M., Fetch Engines and Databases, 3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3). 2000.
G. Yalcin, Unsal, O., Cristal, A., and Valero, M., FaulTM-multi: Fault Tolerance for Multithreaded Applications Running on Transactional Memory Hardware, Workshop on Wild and Sane Ideas in Speculation and Transactions. Galveston Island, TX, United States, 2011.
E. Quiñones, Abella, J., Cazorla, F., and Valero, M., Exploiting Intra-Task Slack Time of Load Operations for DVFS in Hard Real-Time Multi-core Systems, In Work in Progess (WiP), under the the 24nd Euromicro Conference on Real-Time Systems (ECRTS 2011). 2011.
C. Acosta, Cazorla, F., Ramirez, A., and Valero, M., Core to Memory Interconnection Implications for Forthcoming On-Chip Multiprocessors, 1st Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI 2007). 2007.
E. Akpinar, Tomić, S., Cristal, A., Unsal, O., and Valero, M., A Comprehensive Study of Conflict Resolution Policies in Hardware Transactional Memory, 6th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT). San Jose Convention Center, United States, 2011.
O. J. Santana, Falcón, A., Ramirez, A., and Valero, M., A Complexity-Effective Decoding Architecture Based on Instruction Streams, Workshop on Complexity-Effective Design (WCED). 2004.
A. Vega, Rico, A., Cabarcas, F., Ramirez, A., and Valero, M., Comparing last-level cache designs for CMP architectures, IFMT '10: International Forum on Next-Generation Multicore/Manycore Technologies. 2010.
C. Acosta, Vajapeyam, S., Ramirez, A., and Valero, M., CDE: A Compiler-driven, Dependence-Centric, Eager-executing Architecture for the Billion Transistors Era, Workshop on Complexity-Effective Design (WCED 2003). 2003.
V. J. Jiménez, Cazorla, F., Gioiosa, R., Kursun, E., Isci, C., Buyuktosunoglu, A., and Valero, M., A Case for Energy Aware Accounting in Large Scale Computing Facilities: Cost Metrics and Implications for Processor Design.. Workshop on Architectural Concerns in Large Datacenters (ACLD), in conjunction with ISCA, 2010.
M. Etinski, Corbalán, J., Labarta, J., and Valero, M., BSLD Threshold Driven Power Management Policy for HPC Centers. IEEE International Symposium on Parallel&Distributed Processing, HPPAC workshop, 2010.
J. Torres, Ayguadé, E., Carrera, D., Guitart, J., Beltran, V., Becerra, Y., Badia, R. M., Labarta, J., and Valero, M., BSC contributions in Energy-aware Resource Management for Large Scale Distributed Systems, 1st Year Workshop of the COST Action IC0804 on Energy Efficiency in Large Scale Distributed Systems. pp. 76-79, 2010.
P. Knijnenburg, Ramirez, A., Latorre, F., Larriba-Pey, J. L., and Valero, M., Branch Classification to Control Instruction Fetch in Simultaneous Multithreaded Architectures, International Workshop on Innovative Architecture (IWIA 2002). Kohala Coast, Hawaii (United States), pp. 67-76, 2002.
P. A. Castillo, Mora, A. M., Merelo, J. J., Laredo, J. L., Moreto, M., Cazorla, F., Valero, M., and McKee, S. A., Architecture performance prediction using evolutionary artificial neural networks. In European Workshop on Hardware Optimization Techniques (EVOHot). Napoli, Italy, 2008.
F. Cazorla, Fernández, E., Ramirez, A., and Valero, M., Approaching a Smart Sharing of Resources in SMT Processors, Workshop on Complexity-Effective Design (WCED). 2004.
J. Verdú, García, J., Nemirovsky, M., and Valero, M., Analysis of Traffic Traces for Stateful Applications. NP3 : Third Workshop on Network Processors and Applications at HPCA-10, 2004.
O. J. Santana, Galluzzi, M., Ramirez, A., and Valero, M., An Analysis of Dynamic Instruction Streams, XIV Jornadas de Paralelismo. Leganés (Spain), pp. 527-532, 2003.
M. March, García, J., Cerdá, L., and Valero, M., Analysis of a high performance DRAM/SRAM memory scheme for fast packet buffers. WEPA-1: Workshop on Embedded Parallel Architectures at HPCA-10, 2004.
D. Prat, Ortega, C., Casas, M., Moreto, M., and Valero, M., Adaptive and application dependent runtime guided hardware prefetcher reconfiguration on the IBM POWER7, 6th International Workshop on Adaptive Self-tuning Computing Systems. arXiv.org, Amsterdam, Netherlands, pp. 1–6, 2015.

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