Transactiﬁcation of a real-world system library. 5th ACM SIGPLAN Workshop on Transactional Computing - TRANSACT 2010 (2010).
Transaction Coalescing - Lowering Transactional Overheads by Merging Transactions. Sixth Workshop on Programmability Issues for Heterogeneous Multicores (MULTIPROG-2013) (2013).
Task Superscalar: Using Processors as Functional Units. USENIX Workshop on Hot Topics In Parallelism (HotPar) (2010).
Semi-static Branch Prediction for Optimized Code Layouts. 3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3) (2000).
Scalability Analysis of Progressive Alignment in a Multicore. International Workshop on Multi-Core Computing Systems (MuCoCoS 2010) (2010).
Reducing Fetch Architecture Complexity Using Procedure Inlining. 8th Workshop on Interaction between Compilers and Computer Architectures (INTERACT) (2004).
Performance Impact of the Interconnection Network on MareNostrum Applications. 1st Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC 2007) (2007).
Object Orienteed Execution Model (OOM). 2nd Workshop on New Directions in Computer Architecture (NDCA-2) Held in Conjunction with the 38th International Symposium on Computer Architecture (ISCA-38) (2011). at <http://ndca2.saclay.inria.fr/papers/markovic.pdf>
Object Oriented execution Model (OOM). New Directions in Computer Architecture (NDCA-2) (2011).
Latency Tolerant Branch Predictors. 2003 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'03) 30-39 (2003).
J-DSE: Joint Software and Hardware Design Space Exploration for Application Specific Processors. (2010).
Integrating Dataflow Abstractions into Transactional Memory. First Workshop on Systems for Future Multi-Core Architectures (SFMA'11) 1–6 (2011).
Hierarchical Gaussian Topologies. (2005).
Hardware/Software Techniques for Assisted Execution Runtime Systems. The 2nd Workshop on Runtime Environments, Systems, Layering and Virtualized Environments (RESoLVE) (2012).
Fetch Engines and Databases. 3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3) (2000).
FaulTM-multi: Fault Tolerance for Multithreaded Applications Running on Transactional Memory Hardware. Workshop on Wild and Sane Ideas in Speculation and Transactions (2011).
Exploiting Intra-Task Slack Time of Load Operations for DVFS in Hard Real-Time Multi-core Systems. In Work in Progess (WiP), under the the 24nd Euromicro Conference on Real-Time Systems (ECRTS 2011) (2011).
Core to Memory Interconnection Implications for Forthcoming On-Chip Multiprocessors. 1st Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI 2007) (2007).
A Comprehensive Study of Conflict Resolution Policies in Hardware Transactional Memory. 6th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT) (2011).
A Complexity-Effective Decoding Architecture Based on Instruction Streams. Workshop on Complexity-Effective Design (WCED) (2004).
Comparing last-level cache designs for CMP architectures. IFMT '10: International Forum on Next-Generation Multicore/Manycore Technologies (2010).
CDE: A Compiler-driven, Dependence-Centric, Eager-executing Architecture for the Billion Transistors Era. Workshop on Complexity-Effective Design (WCED 2003) (2003).
A Case for Energy Aware Accounting in Large Scale Computing Facilities: Cost Metrics and Implications for Processor Design. (2010).
BSC contributions in Energy-aware Resource Management for Large Scale Distributed Systems. 1st Year Workshop of the COST Action IC0804 on Energy Efficiency in Large Scale Distributed Systems 76-79 (2010).
Branch Classification to Control Instruction Fetch in Simultaneous Multithreaded Architectures. International Workshop on Innovative Architecture (IWIA 2002) 67-76 (2002).
Approaching a Smart Sharing of Resources in SMT Processors. Workshop on Complexity-Effective Design (WCED) (2004).
An Analysis of Dynamic Instruction Streams. XIV Jornadas de Paralelismo 527-532 (2003).
Task Management Analysis on the Cell BE. XIX Jornadas de Paralelismo, pp. 271-276, Castellón (Spain) 271-276 (2008).
Selecting Where to Simulate SPEC2000 Using Streams Analysis. XV Jornadas de Paralelismo 208--213 (2004).
Scalability and Complexity of 2-Dimensional SIMD Extensions. XV Jornadas de Paralelismo 190-195 (2004).
Predicting two Streams per Cycle. XVI Jornadas de Paralelismo 3-10 (2005).
Online Prediction of Throughput for Different Cache Sizes. XVIII Jornadas de Paralelismo (2007).
Metrics for the Evaluation of SMT Processors Performance. XVI Jornadas de Paralelismo (2005).