Publications

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Workshops
Valero, M., Verdú, J., Nemirovsky, M. & García, J. Workload Characterization and Stateful Networking Aplications. (2005).
Cakarevic, V. et al. Understanding the overhead of the spin-lock loop in CMT architectures. (2008).
Miletić, N. et al. Transactification of a real-world system library. 5th ACM SIGPLAN Workshop on Transactional Computing - TRANSACT 2010 (2010).
Smiljkovic, V., Stipić, S., Unsal, O., Cristal, A. & Valero, M. Transaction Coalescing - Lowering Transactional Overheads by Merging Transactions. Sixth Workshop on Programmability Issues for Heterogeneous Multicores (MULTIPROG-2013) (2013).
Verdú, J., Nemirovsky, M., García, J. & Valero, M. Traffic Aggregation Impact on the Memory Performance of Networking Applications. (2004).
Verdú, J., Nemirovsky, M., García, J. & Valero, M. Te Impact of Traffic Aggregation on the Memory Performance of Networking Applications. (2005).
Etsion, Y. et al. Task Superscalar: Using Processors as Functional Units. USENIX Workshop on Hot Topics In Parallelism (HotPar) (2010).
Pajuelo, A., González, A. & Valero, M. Speculative Execution for Hiding Memory Latency. (2004).
Ramírez, T., Pajuelo, M., Santana, O. J. & Valero, M. A Simple Speculative Load Control Mechanism for Energy Saving. (2006).
Ramirez, A., Larriba-Pey, J. L. & Valero, M. Semi-static Branch Prediction for Optimized Code Layouts. 3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3) (2000).
Isaza, S., Sánchez, F., Gaydadjiev, G. N., Ramirez, A. & Valero, M. Scalability Analysis of Progressive Alignment in a Multicore. International Workshop on Multi-Core Computing Systems (MuCoCoS 2010) (2010).
Santana, O. J., Ramirez, A. & Valero, M. Reducing Fetch Architecture Complexity Using Procedure Inlining. 8th Workshop on Interaction between Compilers and Computer Architectures (INTERACT) (2004).
Kedzierski, K., Cazorla, F., Gioiosa, R., Buyuktosunoglu, A. & Valero, M. Power and Performance Aware Reconfigurable Cache for CMPs. (2010).
Ramirez, A., Prat, O., Labarta, J. & Valero, M. Performance Impact of the Interconnection Network on MareNostrum Applications. 1st Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC 2007) (2007).
Markovic, N. et al. Object Orienteed Execution Model (OOM). 2nd Workshop on New Directions in Computer Architecture (NDCA-2) Held in Conjunction with the 38th International Symposium on Computer Architecture (ISCA-38) (2011). at <http://ndca2.saclay.inria.fr/papers/markovic.pdf>
Markovic, N. et al. Object Oriented execution Model (OOM). New Directions in Computer Architecture (NDCA-2) (2011).
Vera, J. et al. A Novel Evaluation Methodology to Obtain Fair Measurements in Multithreaded Architectures. (2006).
Vera, J. et al. Measuring the Performance of Multithreaded Processors. (2007).
Alastruey, J. J., Monreal, T., Viñals, V. & Valero, M. Limits on Early Release of Physical Registers. (2004).
Santana, O. J., Ramirez, A. & Valero, M. Latency Tolerant Branch Predictors. 2003 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'03) 30-39 (2003).
Paolieri, M., Bonesana, I., Gioiosa, R. & Valero, M. J-DSE: Joint Software and Hardware Design Space Exploration for Application Specific Processors. (2010).
Gajinov, V. et al. Integrating Dataflow Abstractions into Transactional Memory. First Workshop on Systems for Future Multi-Core Architectures (SFMA'11) 1–6 (2011).
García, J., March, M., Cerdá, L., Corbal, J. & Valero, M. A Hybrid DRAM/SRAM Design for Fast Packet Buffers. (2004).
Moreto, M., Martínez, C., Beivide, R., Vallejo, E. & Valero, M. Hierarchical Gaussian Topologies. (2005).
Kestor, G., Gioiosa, R., Unsal, O., Cristal, A. & Valero, M. Hardware/Software Techniques for Assisted Execution Runtime Systems. The 2nd Workshop on Runtime Environments, Systems, Layering and Virtualized Environments (RESoLVE) (2012).
Moreto, M. et al. Hard Real-Time Capable Multicore Processors for Space Applications. (2010).
Navarro, C., Ramirez, A., Larriba-Pey, J. L. & Valero, M. Fetch Engines and Databases. 3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3) (2000).
Yalcin, G., Unsal, O., Cristal, A. & Valero, M. FaulTM-multi: Fault Tolerance for Multithreaded Applications Running on Transactional Memory Hardware. Workshop on Wild and Sane Ideas in Speculation and Transactions (2011).
Quiñones, E., Abella, J., Cazorla, F. & Valero, M. Exploiting Intra-Task Slack Time of Load Operations for DVFS in Hard Real-Time Multi-core Systems. In Work in Progess (WiP), under the the 24nd Euromicro Conference on Real-Time Systems (ECRTS 2011) (2011).
Acosta, C., Cazorla, F., Ramirez, A. & Valero, M. Core to Memory Interconnection Implications for Forthcoming On-Chip Multiprocessors. 1st Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI 2007) (2007).
Akpinar, E., Tomić, S., Cristal, A., Unsal, O. & Valero, M. A Comprehensive Study of Conflict Resolution Policies in Hardware Transactional Memory. 6th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT) (2011).
Santana, O. J., Falcón, A., Ramirez, A. & Valero, M. A Complexity-Effective Decoding Architecture Based on Instruction Streams. Workshop on Complexity-Effective Design (WCED) (2004).
Vega, A., Rico, A., Cabarcas, F., Ramirez, A. & Valero, M. Comparing last-level cache designs for CMP architectures. IFMT '10: International Forum on Next-Generation Multicore/Manycore Technologies (2010).
Acosta, C., Vajapeyam, S., Ramirez, A. & Valero, M. CDE: A Compiler-driven, Dependence-Centric, Eager-executing Architecture for the Billion Transistors Era. Workshop on Complexity-Effective Design (WCED 2003) (2003).
Jiménez, V. J. et al. A Case for Energy Aware Accounting in Large Scale Computing Facilities: Cost Metrics and Implications for Processor Design. (2010).
Etinski, M., Corbalán, J., Labarta, J. & Valero, M. BSLD Threshold Driven Power Management Policy for HPC Centers. (2010).
Torres, J. et al. BSC contributions in Energy-aware Resource Management for Large Scale Distributed Systems. 1st Year Workshop of the COST Action IC0804 on Energy Efficiency in Large Scale Distributed Systems 76-79 (2010).
Knijnenburg, P., Ramirez, A., Latorre, F., Larriba-Pey, J. L. & Valero, M. Branch Classification to Control Instruction Fetch in Simultaneous Multithreaded Architectures. International Workshop on Innovative Architecture (IWIA 2002) 67-76 (2002).
Castillo, P. A. et al. Architecture performance prediction using evolutionary artificial neural networks. (2008).
Cazorla, F., Fernández, E., Ramirez, A. & Valero, M. Approaching a Smart Sharing of Resources in SMT Processors. Workshop on Complexity-Effective Design (WCED) (2004).
Verdú, J., García, J., Nemirovsky, M. & Valero, M. Analysis of Traffic Traces for Stateful Applications. (2004).
Santana, O. J., Galluzzi, M., Ramirez, A. & Valero, M. An Analysis of Dynamic Instruction Streams. XIV Jornadas de Paralelismo 527-532 (2003).
March, M., García, J., Cerdá, L. & Valero, M. Analysis of a high performance DRAM/SRAM memory scheme for fast packet buffers. (2004).

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