Publications

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Zyulkyarov, F., Unsal, O., Cristal, A. & Valero, M. Synthetic Workloads for Transactional Memory. 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07) 135–137 (2007).
Yalcin, G., Unsal, O., Cristal, A., Hur, I. & Valero, M. SymptomTM: Symptom Based Error Detection and Recovery Using Hardware Transactional Memory. Parallel Architectures and Compilation Techniques (PACT) 199–200 (2011).
Rajovic, N., Carpenter, P., Gelado, I., Puzovic, N., Ramirez, A. & Valero, M. Supercomputing with commodity CPUs: are mobile SoCs ready for HPC?. SC13: International Conference for High Performance Computing, Networking, Storage and Analysis 40–40 (2013).
Falcón, A., Santana, O.J., Medina, P., Fernández, E., Ramirez, A. & Valero, M. Studying New Ways for Improving Adaptive History Length Branch Predictors. 4th International Symposium on High Performance Computing (ISHPC-4) 271-279 (2002).
Ramirez, A., Larriba-Pey, J.L. & Valero, M. A Stream Processor Front-end. IEEE Technical Committee on Computer Architecture Newsletter 10-13 (2000).
Santana, O.J., Falcón, A., Ramirez, A. & Valero, M. Stream Predictor Guided Instruction Decoding. XV Jornadas de Paralelismo 184-189 (2004).
Kestor, G., Gioiosa, R., Harris, T., Cristal, A., Unsal, O., Valero, M. & Hur, I. STM2: A Parallel STM for High Performance Simultaneous Multi-Threading Systems. The 20th IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT) (2011).
Pajuelo, A., González, A. & Valero, M. Speculative Execution for Hiding Memory Latency. (2005).
Pajuelo, A., González, A. & Valero, M. Speculative Execution for Hiding Memory Latency. (2004).
Alastruey, J.J., Monreal, T., Viñals, V. & Valero, M. Speculative Early Register Release. (2006).
Boneti, C., Cazorla, F., Gioiosa, R., Cher, C.-Y., Buyuktosunoglu, A. & Valero, M. Software-Controlled Priority Characterization of POWER5 Processor. (2008).at <http://www2.computer.org/portal/web/csdl/doi/10.1109/ISCA.2008.8>
Sönmez, N., Perfumo, C., Stipić, S., Harris, T., Unsal, O., Cristal, A. & Valero, M. Software Transactional Memory Implementation. Advanced Computer Architecture and Computation for Embedded Systems (ACACES 2009) 101–103 (2009).
Ramirez, A., Larriba-Pey, J.L., Navarro, C., Valero, M. & Torrellas, J. Software Trace Cache for Commercial Applications. International Journal of Parallel Programming 30, 373-395 (2002).
Ramirez, A., Larriba-Pey, J.L., Navarro, C., Torrellas, J. & Valero, M. Software Trace Cache. International Conference on Supercomputing (ICS'1999) 119-126 (1999).
Ramirez, A., Larriba-Pey, J.L. & Valero, M. Software Trace Cache. IEEE Transactions on Computers 54, 22-35 (2005).
Zalamea, J., Llosa, J., Ayguadé, E. & Valero, M. Software and Hardware Techniques to Optimize Register File Utilization in VLIW. (2004).
Morari, A., Boneti, C., Cazorla, F.J., Gioiosa, R., Cher, C.-Y., Buyuktosunoglu, A., Bose, P. & Valero, M. SMT Malleability in IBM POWER5 and POWER6 Processors. IEEE Transactions on Computers 00, (2012).
Rico, A., Cabarcas, F., Villavieja, C., Pavlovic, M., Vega, A., Etsion, Y., Ramirez, A. & Valero, M. On the Simulation of Large-scale Architectures Using Multiple Application Abstraction Levels. ACM Transactions on Architecture and Code Optimization 8, 36 (2012).
Subotic, V., Sancho, J.C., Labarta, J. & Valero, M. A simulation framework to automatically analyze the communication-computation overlap in scientific applications. (2011).
Subotic, V., Labarta, J. & Valero, M. Simulation environment to study overlapping of communication and computation. (2011).
González, J., Giménez, J., Casas, M., Moretó, M., Ramirez, A., Labarta, J. & Valero, M. Simulating Whole Supercomputer Applications. IEEE Micro 31, 32-45 (2011).
Ramírez, T., Pajuelo, M., Santana, O.J. & Valero, M. A Simple Speculative Load Control Mechanism for Energy Saving. (2006).
Ramírez, M.A., Cristal, A., Veidenbaum, A., Villa, L.A. & Valero, M. A Simple Low-Energy Instruction Wakeup Mechanism. 5th International Symposium on High Performance Computing (ISHPC-V) 99–112 (2003).
Armejach, A., Seyedi, A., Gil, R.T.J., Hur, I., Unsal, O., Cristal, A. & Valero, M. ShadowHTM: Using a dual-bitcell L1 Data Cache to Improve Hardware Transactional Memory Performance. (2010).
Ramirez, A., Larriba-Pey, J.L. & Valero, M. Semi-static Branch Prediction for Optimized Code Layouts. 3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3) (2000).
Alastruey, J.J., Cazorla, F., Monreal, T., Viñals, V. & Valero, M. Selection of the Register File Size and the Resource Allocation Policy on SMT Processors. (2008).
ivan Ratkovic,, Palomar, O., milan stanic,, Unsal, O., Cristal, A. & Valero, M. On the Selection of Adder Unit in Energy Efficient Vector Processing. 14th International Symposium on Quality Electronic Design (ISQED) (2013).
Falcón, A., Santana, O.J., Ramirez, A. & Valero, M. Selecting Where to Simulate SPEC2000 Using Streams Analysis. XV Jornadas de Paralelismo 208--213 (2004).
Boneti, C., Cazorla, F., Gioiosa, R. & Valero, M. Scheduling Real-Time Systems With Explicit Resource Allocation Processors. (2008).
Sánchez, F., Cabarcas, F., Ramirez, A. & Valero, M. Scalable multicore architectures for long DNA sequence comparison. Concurrency and Computation Practice and Experience 23, (2011).
González, R., Cristal, A., Pericàs, M., Veidenbaum, A. & Valero, M. Scalable Distributed Register File. 5th Workshop on Complexity-Effective Design 5–14 (2004).
Álvarez, M., Ramirez, A., Meenderinck, C., Juurlink, B. & Valero, M. Scalability of Macroblock-level parallelism for H.264 decoding. The Fifteenth International Conference on Parallel and Distributed Systems (ICPADS'09) (2009).
Álvarez, M., Ramirez, A., Martorell, X., Ayguadé, E. & Valero, M. Scalability of Macroblock-level Parallelism for H.264 Decoding. Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008, Poster 59-62 (2008).
Sánchez, F., Álvarez, M., Salami, E., Ramirez, A. & Valero, M. On the Scalability of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications. 2005 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2005) 167-176 (2005).at <http://www.bsc.es/media/404.pdf>
Álvarez, M., Sánchez, F., Salami, E., Ramirez, A. & Valero, M. Scalability and Complexity of 2-Dimensional SIMD Extensions. XV Jornadas de Paralelismo 190-195 (2004).
Isaza, S., Sánchez, F., Gaydadjiev, G.N., Ramirez, A. & Valero, M. Scalability Analysis of Progressive Alignment on a Multicore. Fourth International Conference on Complex, Intelligent and Software Intensive Systems (CISIS '10) 889-894 (2010).at <http://dx.doi.org/10.1109/CISIS.2010.149>
Isaza, S., Sánchez, F., Gaydadjiev, G.N., Ramirez, A. & Valero, M. Scalability Analysis of Progressive Alignment in a Multicore. International Workshop on Multi-Core Computing Systems (MuCoCoS 2010) (2010).