Publications

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F. Zyulkyarov, Unsal, O., Cristal, A., and Valero, M., Synthetic Workloads for Transactional Memory, in 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07), L'Aquila, Italy, 2007, pp. 135–137.
G. Yalcin, Unsal, O., Cristal, A., Hur, I., and Valero, M., SymptomTM: Symptom Based Error Detection and Recovery Using Hardware Transactional Memory, Parallel Architectures and Compilation Techniques (PACT). Galveston Island, United States, pp. 199–200, 2011.
N. Rajovic, Carpenter, P., Gelado, I., Puzovic, N., Ramirez, A., and Valero, M., Supercomputing with commodity CPUs: are mobile SoCs ready for HPC?, SC13: International Conference for High Performance Computing, Networking, Storage and Analysis. Denver, United States, pp. 40–40, 2013.
A. Falcón, Santana, O. J., Medina, P., Fernández, E., Ramirez, A., and Valero, M., Studying New Ways for Improving Adaptive History Length Branch Predictors, 4th International Symposium on High Performance Computing (ISHPC-4). Kansai Science City (Japan), pp. 271-279, 2002.
A. Ramirez, Larriba-Pey, J. L., and Valero, M., A Stream Processor Front-end, IEEE Technical Committee on Computer Architecture Newsletter. pp. 10-13, 2000.
O. J. Santana, Falcón, A., Ramirez, A., and Valero, M., Stream Predictor Guided Instruction Decoding, XV Jornadas de Paralelismo. pp. 184-189, 2004.
G. Kestor, Gioiosa, R., Harris, T., Cristal, A., Unsal, O., Valero, M., and Hur, I., STM2: A Parallel STM for High Performance Simultaneous Multi-Threading Systems, The 20th IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT). 2011.
T. Hussain, Palomar, O., Unsal, O., Cristal, A., Ayguadé, E., Valero, M., and Haider, A., Stand-alone Memory Controller for Graphics System, in The 10th International Symposium on Applied Reconfigurable Computing (ARC 2014), Porto, Portugal, 2014.
A. Pajuelo, González, A., and Valero, M., Speculative Execution for Hiding Memory Latency. MEDEA Workshop: ?MEmory performance:DEaling with Applications, systems and architecture, 2004.
A. Pajuelo, González, A., and Valero, M., Speculative Execution for Hiding Memory Latency. Computer Architecture News, 2005.
J. J. Alastruey, Monreal, T., Viñals, V., and Valero, M., Speculative Early Register Release. ACM International Conference on Computing Frontiers, 2006.
C. Boneti, Cazorla, F., Gioiosa, R., Cher, C. - Y., Buyuktosunoglu, A., and Valero, M., Software-Controlled Priority Characterization of POWER5 Processor. Beijing, China, 2008.
N. Sönmez, Perfumo, C., Stipić, S., Harris, T., Unsal, O., Cristal, A., and Valero, M., Software Transactional Memory Implementation, in Advanced Computer Architecture and Computation for Embedded Systems (ACACES 2009), Terrassa, Spain, 2009, pp. 101–103.
A. Ramirez, Larriba-Pey, J. L., Navarro, C., Valero, M., and Torrellas, J., Software Trace Cache for Commercial Applications, International Journal of Parallel Programming, vol. 30, no. 5. pp. 373-395, 2002.
A. Ramirez, Larriba-Pey, J. L., Navarro, C., Torrellas, J., and Valero, M., Software Trace Cache, International Conference on Supercomputing (ICS'1999). pp. 119-126, 1999.
A. Ramirez, Larriba-Pey, J. L., and Valero, M., Software Trace Cache, IEEE Transactions on Computers, vol. 54, no. 1. pp. 22-35, 2005.
J. Zalamea, Llosa, J., Ayguadé, E., and Valero, M., Software and Hardware Techniques to Optimize Register File Utilization in VLIW. International Journal of Parallel Programming, 2004.
A. Morari, Boneti, C., Cazorla, F. J., Gioiosa, R., Cher, C. - Y., Buyuktosunoglu, A., Bose, P., and Valero, M., SMT Malleability in IBM POWER5 and POWER6 Processors, IEEE Transactions on Computers, vol. 00. 2012.
A. Rico, Cabarcas, F., Villavieja, C., Pavlovic, M., Vega, A., Etsion, Y., Ramirez, A., and Valero, M., On the Simulation of Large-scale Architectures Using Multiple Application Abstraction Levels, ACM Transactions on Architecture and Code Optimization, vol. 8. p. 36, 2012.
V. Subotic, Sancho, J. C., Labarta, J., and Valero, M., A simulation framework to automatically analyze the communication-computation overlap in scientific applications. IEEE International Conference on Cluster Computing, 2011.
V. Subotic, Sancho, J. C., Labarta, J., and Valero, M., A Simulation Framework to Automatically Analyze the Communication-Computation Overlap in Scientific Applications, Cluster Computing (CLUSTER), 2010 IEEE International Conference on. pp. 275-283, 2010.
V. Subotic, Labarta, J., and Valero, M., Simulation environment to study overlapping of communication and computation. IEEE International Symposium on Performance Analysis of Systems and Software, 2011.
J. González, Giménez, J., Casas, M., Moretó, M., Ramirez, A., Labarta, J., and Valero, M., Simulating Whole Supercomputer Applications, IEEE Micro, vol. 31. IEEE, pp. 32-45, 2011.
T. Ramírez, Pajuelo, M., Santana, O. J., and Valero, M., A Simple Speculative Load Control Mechanism for Energy Saving. MEDEA Workshop: ?MEmory performance:DEaling with Applications, systems and architecture?, 2006.
M. A. Ramírez, Cristal, A., Veidenbaum, A., Villa, L. A., and Valero, M., A Simple Low-Energy Instruction Wakeup Mechanism, in 5th International Symposium on High Performance Computing (ISHPC-V), Tokio, Japan, 2003, pp. 99–112.
A. Armejach, Seyedi, A., Gil, R. T. J., Hur, I., Unsal, O., Cristal, A., and Valero, M., ShadowHTM: Using a dual-bitcell L1 Data Cache to Improve Hardware Transactional Memory Performance. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, 2010.
A. Ramirez, Larriba-Pey, J. L., and Valero, M., Semi-static Branch Prediction for Optimized Code Layouts, 3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3). 2000.
J. J. Alastruey, Cazorla, F., Monreal, T., Viñals, V., and Valero, M., Selection of the Register File Size and the Resource Allocation Policy on SMT Processors. In 20th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). Campo Grande, Brazil, 2008.
Ivan Ratkovic, Palomar, O., Milan Stanic,, Unsal, O., Cristal, A., and Valero, M., On the Selection of Adder Unit in Energy Efficient Vector Processing, 14th International Symposium on Quality Electronic Design (ISQED). Santa Clara, United States, 2013.
A. Falcón, Santana, O. J., Ramirez, A., and Valero, M., Selecting Where to Simulate SPEC2000 Using Streams Analysis, XV Jornadas de Paralelismo. p. 208--213, 2004.
C. Boneti, Cazorla, F., Gioiosa, R., and Valero, M., Scheduling Real-Time Systems With Explicit Resource Allocation Processors. In International Conference on Architecture of Computing Systems (ARCS). Dresden, Germany, 2008.
F. Sánchez, Cabarcas, F., Ramirez, A., and Valero, M., Scalable multicore architectures for long DNA sequence comparison, Concurrency and Computation Practice and Experience, vol. 23, no. 17. 2011.
R. González, Cristal, A., Pericàs, M., Veidenbaum, A., and Valero, M., Scalable Distributed Register File, in 5th Workshop on Complexity-Effective Design, München, Germany, 2004, pp. 5–14.
M. Álvarez, Ramirez, A., Martorell, X., Ayguadé, E., and Valero, M., Scalability of Macroblock-level Parallelism for H.264 Decoding, Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008, Poster. pp. 59-62, 2008.
M. Álvarez, Ramirez, A., Meenderinck, C., Juurlink, B., and Valero, M., Scalability of Macroblock-level parallelism for H.264 decoding, The Fifteenth International Conference on Parallel and Distributed Systems (ICPADS'09). Shenzhen (China), 2009.
F. Sánchez, Álvarez, M., Salami, E., Ramirez, A., and Valero, M., On the Scalability of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications, 2005 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2005). pp. 167-176, 2005.
M. Álvarez, Sánchez, F., Salami, E., Ramirez, A., and Valero, M., Scalability and Complexity of 2-Dimensional SIMD Extensions, XV Jornadas de Paralelismo. pp. 190-195, 2004.
S. Isaza, Sánchez, F., Gaydadjiev, G. N., Ramirez, A., and Valero, M., Scalability Analysis of Progressive Alignment on a Multicore, Fourth International Conference on Complex, Intelligent and Software Intensive Systems (CISIS '10). pp. 889-894, 2010.
S. Isaza, Sánchez, F., Gaydadjiev, G. N., Ramirez, A., and Valero, M., Scalability Analysis of Progressive Alignment in a Multicore, International Workshop on Multi-Core Computing Systems (MuCoCoS 2010). Krakow (Poland), 2010.