Publications

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Markovic, N. et al. Object Oriented execution Model (OOM). New Directions in Computer Architecture (NDCA-2) (2011).
Markovic, N. et al. Object Orienteed Execution Model (OOM). 2nd Workshop on New Directions in Computer Architecture (NDCA-2) Held in Conjunction with the 38th International Symposium on Computer Architecture (ISCA-38) (2011). at <http://ndca2.saclay.inria.fr/papers/markovic.pdf>
Moreto, M., Cazorla, F., Ramirez, A. & Valero, M. Online Prediction of Applications Cache Utility. International Symposium on Systems, Architectures, MOdeling and Simulation (SAMOS) 169-177 (2007).
Moreto, M., Cazorla, F., Ramirez, A. & Valero, M. Online Prediction of Throughput for Different Cache Sizes. XVIII Jornadas de Paralelismo (2007).
Radojkovic, P. et al. Optimal Task Assignment in Multithreaded Processors: A Statistical Approach. Architectural Support for Programming Languages and Operating Systems (ASPLOS) (2012).
Radojkovic, P. et al. Optimal Task Assignment in Multithreaded Processors: A Statistical Approach. 17th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-2012) (2012). at <http://capinfo.e.ac.upc.edu/PDFs/dir00/file003944.pdf>
Cristal, A., Martínez, J. F., Llosa, J. & Valero, M. Optimal Use of Registers in Aggressive Superscalar Processors. XIV Jornadas de Paralelismo 553–558 (2003).
Ramirez, A. et al. Optimization of Instruction Fetch for Decision Support Workloads. International Conference on Parallel Processing 238-245 (1999).
Pericàs, M., González, R., Cristal, A., Veidenbaum, A. & Valero, M. An Optimized Front-End Physical Register File with Banking and Writeback Filtering. Workshop on Power-Aware Computer Systems (PACS'04) 4–13 (2004).
Ramirez, A. et al. Optimizing Instruction Fetch for Decision Support Workloads. 2nd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-2) (1999).
Etinski, M., Corbalán, J., Labarta, J. & Valero, M. Optimizing Job Performance Under a Given Power Constraint In HPC Centers. (2010).
Cazorla, F., Fernández, E., Ramirez, A. & Valero, M. Optimizing Long-Latency-Load-Aware Fetch Policies for SMT Processors. International Journal of High Performance Computing and Networking (IJHPCN) 2, (2004).
Cristal, A., Ortega, D., Llosa, J. & Valero, M. Out-of-Order Commit Processors. 10th International Symposium on High Performance Computer Architecture (HPCA-10) 48–59 (IEEE Computer Society Press, 2004).
Cristal, A., Martínez, J. F., Ortega, D., Llosa, J. & Valero, M. Out-of-Order Commit Processors. (2003).
Pericàs, M., González, R., Cristal, A. & Valero, M. Overcoming the Memor Wall with D-KIPs. 2005 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-2005) 99–102 (Academia Press, 2005).
Marjanovic, V., Labarta, J., Ayguadé, E. & Valero, M. Overlapping Communication and Computation by Using a Hybrid MPI/SMPSs Approach. (2010).