Publications

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N. Markovic, Nemirovsky, D., González, R., Unsal, O., Valero, M., and Cristal, A., Object Oriented execution Model (OOM), New Directions in Computer Architecture (NDCA-2). San Jose, California, United States, 2011.
N. Markovic, Nemirovsky, D., González, R., Ünsal, O. S., Valero, M., and Cristal, A., Object Orienteed Execution Model (OOM), 2nd Workshop on New Directions in Computer Architecture (NDCA-2) Held in Conjunction with the 38th International Symposium on Computer Architecture (ISCA-38). San Jose, California, Sunday June 5th, 2011.
M. Moreto, Cazorla, F., Ramirez, A., and Valero, M., Online Prediction of Applications Cache Utility, International Symposium on Systems, Architectures, MOdeling and Simulation (SAMOS). IEEE Computer Society Press, pp. 169-177, 2007.
M. Moreto, Cazorla, F., Ramirez, A., and Valero, M., Online Prediction of Throughput for Different Cache Sizes, XVIII Jornadas de Paralelismo. Zaragoza, Spain, 2007.
P. Radojkovic, Cakarevic, V., Moreto, M., Verdu, J., Pajuelo, A., Cazorla, F., Nemirovsky, M., and Valero, M., Optimal Task Assignment in Multithreaded Processors: A Statistical Approach, Architectural Support for Programming Languages and Operating Systems (ASPLOS). ACM, 2012.
P. Radojkovic, Cakarevic, V., Moretó, M., Verdú, J., Pajuelo, A., Cazorla, F. J., Nemirovsky, M., and Valero, M., Optimal Task Assignment in Multithreaded Processors: A Statistical Approach, 17th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-2012). London, United Kingdom, 2012.
A. Cristal, Martínez, J. F., Llosa, J., and Valero, M., Optimal Use of Registers in Aggressive Superscalar Processors, XIV Jornadas de Paralelismo. Leganés, Spain, pp. 553–558, 2003.
A. Ramirez, Larriba-Pey, J. L., Navarro, C., Serrano, X., Torrellas, J., and Valero, M., Optimization of Instruction Fetch for Decision Support Workloads, International Conference on Parallel Processing. pp. 238-245, 1999.
M. Pericàs, González, R., Cristal, A., Veidenbaum, A., and Valero, M., An Optimized Front-End Physical Register File with Banking and Writeback Filtering, Workshop on Power-Aware Computer Systems (PACS'04). Portland, OR, United States, pp. 4–13, 2004.
A. Ramirez, Larriba-Pey, J. L., Navarro, C., Serrano, X., Torrellas, J., and Valero, M., Optimizing Instruction Fetch for Decision Support Workloads, 2nd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-2). 1999.
M. Etinski, Corbalán, J., Labarta, J., and Valero, M., Optimizing Job Performance Under a Given Power Constraint In HPC Centers. International Green Computing Conference, 2010.
F. Cazorla, Fernández, E., Ramirez, A., and Valero, M., Optimizing Long-Latency-Load-Aware Fetch Policies for SMT Processors, International Journal of High Performance Computing and Networking (IJHPCN), vol. 2, no. 2. 2004.
A. Cristal, Ortega, D., Llosa, J., and Valero, M., Out-of-Order Commit Processors, 10th International Symposium on High Performance Computer Architecture (HPCA-10). IEEE Computer Society Press, Madrid, Spain, pp. 48–59, 2004.
A. Cristal, Martínez, J. F., Ortega, D., Llosa, J., and Valero, M., Out-of-Order Commit Processors. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2003.
M. Pericàs, González, R., Cristal, A., and Valero, M., Overcoming the Memor Wall with D-KIPs, 2005 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-2005). Academia Press, L'Aquila, Italy, pp. 99–102, 2005.
V. Marjanovic, Labarta, J., Ayguadé, E., and Valero, M., Overlapping Communication and Computation by Using a Hybrid MPI/SMPSs Approach. 24th International Conference on Supercomputing. Epochal Tsukuba, Tsukuba, Japan, 2010.