Publications

Export 14 results:
Sort by: Author [ Title (Desc)] Type Year
Filters: Author is Mateo Valero and First Letter Of Title is M  [Clear All Filters]
A B C D E F G H I J K L [M] N O P Q R S T U V W X Y Z   [Show ALL]
M
Milovanovic, M., Ferrer, R., Gajinov, V., Unsal, O., Cristal, A., Ayguadé, E. & Valero, M. Multithreaded software transactional memory and OpenMP. 8th MEDEA Workshop Memory Performance: Dealing With Applications, Systems And Architecture (MEDEA 2007) 81–88 (2007).at <http://capinfo.e.ac.upc.edu/PDFs/dir22/file003647.pdf>
González, I., Galluzzi, M., Cristal, A. & Valero, M. Multi-State Processor: Arquitectura sin ROB y con recuperaciones Precisas. II Congreso Español de Informática (CEDI 2007) (2007).
González, I., Galluzzi, M., Cristal, A. & Valero, M. The Multi-State Processor. 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07) 127–130 (2007).
Santana, O.J., Ramirez, A. & Valero, M. Multiple Stream Prediction. ISHPC. International Symposium on High Performance Computers (2005).
Nesbit, K.J., Moreto, M., Cazorla, F., Ramirez, A., Valero, M. & Smith, J.E. Multicore Resource Management. IEEE Micro 28, 6-16 (2008).
Moreto, M., Cazorla, F., Ramirez, A. & Valero, M. MLP-aware dynamic cache partitioning. 2008 International Conference on High Performance Embedded Architectures & Compilers (HiPEAC 2008) 337-352 (2008).
Moreto, M., Cazorla, F., Ramirez, A. & Valero, M. MLP-aware dynamic cache partitioning. International Conference on Parallel Architectures and Compilation Techniques (PACT) 418-418 (2007).
Alastruey, J.J., Monreal, T., Viñals, V. & Valero, M. Microarchitectural Support for Speculative Register Renaming. (2006).
Acosta, C., Cazorla, F., Ramirez, A. & Valero, M. MFLUSH: Handling Long-latency loads in SMT On-Chip Multiprocessors. International Conference on Parallel Processing (ICPP) 173-181 (2008).
Mir, S., Cazorla, F., Ramirez, A. & Valero, M. Metrics for the Evaluation of SMT Processors Performance. XVI Jornadas de Paralelismo (2005).
Zyulkyarov, F., Unsal, O., Cristal, A., Milovanovic, M., Ayguadé, E. & Valero, M. Memory Management for Transaction Processing Core in Heterogeneous Chip Multiprocessors. Workshop on Operating System Support for Heterogeneous Multicore Architectures (2007).
Vera, J., Cazorla, F., Pajuelo, A., Santana, O.J., Fernández, E. & Valero, M. Measuring the Performance of Multithreaded Processors. (2007).
Radojkovic, P., Cakarevic, V., Verdú, J., Pajuelo, A., Gioiosa, R., Cazorla, F., Nemirovsky, M. & Valero, M. Measuring Operating System Overhead on CMT Processors. (2008).
Cristal, A., Santana, O.J. & Valero, M. Maintaining Thousands of In-Flight Instructions. 10th International Euro-Par 2004 Conference 9–20 (2004).