Publications

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Luque, C., Moreto, M., Cazorla, F.J. & Valero, M. Fair CPU Time Accounting in CMP+SMT Processors. ACM Trans. Archit. Code Optim. 9, 50:1–50:25 (2013).
Vera, J., Cazorla, F., Pajuelo, A., Santana, O.J., Fernández, E. & Valero, M. FAME: FAirly MEasuring Multithreaded Architectures. (2007).at <http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4336221>
Slamat, B., Nicolaescu, D., Veidenbaum, A. & Valero, M. Fast Speculative Address generation and Way Caching for Reducing L1 data Cache Energy. (2006).
Yalcin, G., Unsal, O., Cristal, A. & Valero, M. FaulTM-multi: Fault Tolerance for Multithreaded Applications Running on Transactional Memory Hardware. Workshop on Wild and Sane Ideas in Speculation and Transactions (2011).
Cazorla, F., Knijnenburg, P., Sakellariou, R., Fernandez, E., Ramirez, A. & Valero, M. Feasibility of QoS for SMT by Resource Allocation. Lecture Notes in Computer Science (LNCS) 3149/2004, (2004).
Navarro, C., Ramirez, A., Larriba-Pey, J.L. & Valero, M. Fetch Engines and Databases. 3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3) (2000).
Ramirez, A., Santana, O.J., Larriba-Pey, J.L. & Valero, M. Fetching Instruction Streams. 35th Annual International Symposium on Microarchitecture (MICRO-35) 371-382 (2002).
Yalcin, G., Unsal, O., Cristal, A. & Valero, M. FIMSIM: A fault injection infrastructure for microarchitectural simulators. 29th International Conference on Computer Design (ICCD) 431–432 (2011).
Galluzzi, M., Puente, V., Cristal, A., Beivide, R., Monasterio, J.A.G. & Valero, M. A first glance at Kilo-instruction based multiprocessors. International Conference on Computing Frontiers 2004 (CF'04) 212–221 (2004).at <http://capinfo.e.ac.upc.edu/PDFs/dir20/file002978.pdf>
González, I., Santana, O.J., Pajuelo, A. & Valero, M. A First Glance at the Implementation of Precise Recoveries in Out-of-order Commit Processors. (2006).
Moreto, M., Cazorla, F., Ramirez, A., Sakellariou, R. & Valero, M. FlexDCP: a QoS framework for CMP architectures. ACM SIGOPS Operating System Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors 43, 0163-5980 (2009).
Moreto, M., Cazorla, F., Ramirez, A., Sakellariou, R. & Valero, M. FlexDCP: a QoS framework for CMP architectures. ACM Operating Systems Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors 43, 86-96 (2010).
Pericàs, M., Cristal, A., Cazorla, F., González, R., Jiménez, D. & Valero, M. A Flexible Heterogeneous Multi-Core Architecture. The 2007 International Conference on Parallel Architectures and Compilation Techniques (PACT 2007) 13–24 (2007).at <http://capinfo.e.ac.upc.edu/PDFs/dir10/file003258.pdf>
Arcas, O., Sönmez, N., Unsal, O., Cristal, A. & Valero, M. A Flexible Hybrid Transactional Memory Multicore on FPGA. Jornadas de Paralelismo 2011 283–289 (2011).
Sönmez, N., Arcas, O., Sayilar, G., Cristal, A., Hur, I., Unsal, O., Singh, S. & Valero, M. From Plasma to BeeFarm: Design Experience of an FPGA-based Multicore Prototype. The 7th International Symposium on Applied Reconfigurable Computing (ARC 2011) 1–10 (2011).
Sonmez, N., Arcas, O., Sayilar, G., Unsal, O., Cristal, A., Hur, I., Singh, S. & Valero, M. From Plasma to BeeFarm: Design Experience of an FPGA-based Multicore Prototype. ARC'11 (2011).
Sonmez, N., Arcas, O., Sayilar, G., Unsal, O., Cristal, A., Hur, I., Singh, S. & Valero, M. From plasma to beefarm: Design experience of an FPGA-based multicore prototype. Reconfigurable Computing: Architectures, Tools and Applications 350–362 (2011).
Cristal, A., Llosa, J., Valero, M. & Ortega, D. Future ILP processors. International Journal of High Performance Computing and Networking 2, 1–10 (2004).
Álvarez, C., Corbal, J. & Valero, M. Fuzzy Memoization for Floating Point Multimedia Applications. (2005).