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Boneti, C. et al. Balancing HPC Applications Through Smart Allocation of Resources in MT Processors. (2008). at <>
Pericàs, M., González, R., Cristal, A., Veidenbaum, A. & Valero, M. Banked Front-End Register File. (2004).
Falcón, A., Stark, J., Ramirez, A., Lai, K. & Valero, M. Better branch prediction through prophet/critic hybrids. IEEE Micro 25, 80-89 (2005).
Pericàs, M. et al. Boosting ILP{&}TLP with the Flexible Multi-Core (FMC). 2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06) 125–128 (Academia Press, 2006).
Knijnenburg, P., Ramirez, A., Larriba-Pey, J. L. & Valero, M. Branch classification for SMT fetch gating. 6th Workshop on Multithreaded Execution, Architecture and Compilation (MTEAC6) (2002).
Knijnenburg, P., Ramirez, A., Latorre, F., Larriba-Pey, J. L. & Valero, M. Branch Classification to Control Instruction Fetch in Simultaneous Multithreaded Architectures. International Workshop on Innovative Architecture (IWIA 2002) 67-76 (2002).
Ramirez, A., Larriba-Pey, J. L. & Valero, M. Branch Prediction Using Profile Data. 7th International Euro-Par Conference (Euro-Par'2001) 386-393 (2001).
Santana, O. J., Falcón, A., Ramirez, A. & Valero, M. Branch Predictor Guided Instruction Decoding. IEEE Intl. Conference on Parallel Architectures and Compiler Techniques (PACT-2006) (2006).
Torres, J. et al. BSC contributions in Energy-aware Resource Management for Large Scale Distributed Systems. 1st Year Workshop of the COST Action IC0804 on Energy Efficiency in Large Scale Distributed Systems 76-79 (2010).
Etinski, M., Corbalán, J., Labarta, J. & Valero, M. BSLD Threshold Driven Power Management Policy for HPC Centers. (2010).