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Filters: Author is Mateo Valero and First Letter Of Title is B  [Clear All Filters]
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C. Boneti, Cazorla, F., Gioiosa, R., Corbalán, J., Labarta, J., and Valero, M., Balancing HPC Applications Through Smart Allocation of Resources in MT Processors. Miami, Florida, USA, 2008.
M. Pericàs, González, R., Cristal, A., Veidenbaum, A., and Valero, M., Banked Front-End Register File. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2004.
A. Falcón, Stark, J., Ramirez, A., Lai, K., and Valero, M., Better branch prediction through prophet/critic hybrids, IEEE Micro, vol. 25, no. 1. pp. 80-89, 2005.
M. Pericàs, Cristal, A., González, R., Cazorla, F., Jiménez, D. A., and Valero, M., Boosting ILP{&}TLP with the Flexible Multi-Core (FMC), 2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06). Academia Press, L'Aquila, Italy, pp. 125–128, 2006.
P. Knijnenburg, Ramirez, A., Larriba-Pey, J. L., and Valero, M., Branch classification for SMT fetch gating, 6th Workshop on Multithreaded Execution, Architecture and Compilation (MTEAC6). Istambul (Turkey), 2002.
P. Knijnenburg, Ramirez, A., Latorre, F., Larriba-Pey, J. L., and Valero, M., Branch Classification to Control Instruction Fetch in Simultaneous Multithreaded Architectures, International Workshop on Innovative Architecture (IWIA 2002). Kohala Coast, Hawaii (United States), pp. 67-76, 2002.
A. Ramirez, Larriba-Pey, J. L., and Valero, M., Branch Prediction Using Profile Data, 7th International Euro-Par Conference (Euro-Par'2001). Manchester (United Kingdom), pp. 386-393, 2001.
O. J. Santana, Falcón, A., Ramirez, A., and Valero, M., Branch Predictor Guided Instruction Decoding, IEEE Intl. Conference on Parallel Architectures and Compiler Techniques (PACT-2006). 2006.
J. Torres, Ayguadé, E., Carrera, D., Guitart, J., Beltran, V., Becerra, Y., Badia, R. M., Labarta, J., and Valero, M., BSC contributions in Energy-aware Resource Management for Large Scale Distributed Systems, 1st Year Workshop of the COST Action IC0804 on Energy Efficiency in Large Scale Distributed Systems. pp. 76-79, 2010.
M. Etinski, Corbalán, J., Labarta, J., and Valero, M., BSLD Threshold Driven Power Management Policy for HPC Centers. IEEE International Symposium on Parallel&Distributed Processing, HPPAC workshop, 2010.